Once a MOSFET's channel has formed, the drain voltage decides how it behaves. With a small drain-to-source voltage, the channel is continuous and the transistor acts like a resistor whose value is set by the gate (the linear or triode region). With a large drain-to-source voltage, the channel pinches off near the drain and the current levels off; the transistor acts like a current source controlled by the gate (the saturation region). Every logic transition passes through both regions.
14 min read | Intermediate Level
What You'll Learn
- The three operating regions of a MOSFET and the conditions for each
- Why the transistor behaves like a resistor in the linear region and a current source in saturation
- How drain current scales with overdrive, and why modern transistors break the square law
- How these regions map onto a logic gate's output transition and its delay
Quick Answer: The Three Regions
| Region | Condition (NMOS) | Channel | Behaves like |
|---|---|---|---|
| Cutoff | V_GS < Vth | None | An open switch (small leakage only) |
| Linear (triode) | V_GS > Vth and V_DS < V_GS - Vth | Continuous from source to drain | A gate-controlled resistor |
| Saturation | V_GS > Vth and V_DS ≥ V_GS - Vth | Pinched off near the drain | A gate-controlled current source |
The boundary between linear and saturation is where V_DS equals the overdrive (V_GS - Vth). This voltage is often written V_DSAT.
The Linear Region: A Gate-Controlled Resistor
When the drain voltage is small, the channel stretches uniformly from source to drain. The drain voltage simply pushes carriers along it, and the current rises in proportion to V_DS - just like a resistor.
The resistance depends on how much charge the channel holds, which depends on overdrive:
Linear region proportion rules (small V_DS) current proportional to overdrive x V_DS channel resistance proportional to 1 / overdrive overdrive x2 -> channel resistance / 2 -> current x2 (same V_DS) width W x2 -> channel resistance / 2 length L x2 -> channel resistance x2
This is the "ON resistance" (R_on) of a switch. Hand calculations of gate delay often model an ON transistor as a resistor R_on charging a capacitor, which is the basis of RC delay estimates.
As V_DS grows, the current rises less steeply than a straight line. The voltage across the channel is no longer negligible compared with the overdrive, so the drain end of the channel becomes thinner. The name "linear" only holds for small V_DS.
Saturation: Pinch-Off and the Current Plateau
The local channel charge depends on how far the gate voltage exceeds the channel voltage at that point. Near the source, that difference is the full overdrive. Near the drain, it is reduced by V_DS. When V_DS reaches the overdrive, the gate no longer has enough "excess" voltage at the drain end to keep the channel inverted. The channel pinches off.
Carriers still reach the drain: they travel along the channel to the pinch-off point and are then swept across the short high-field region by the drain voltage. Beyond pinch-off, raising V_DS further only adds voltage across that small region, so the current barely changes. The transistor now delivers a current set by V_GS, largely independent of V_DS - it behaves as a current source.
The current is not perfectly flat in saturation. As V_DS rises, the pinch-off point moves slightly toward the source, shortening the effective channel. This channel-length modulation gives a small upward slope, which matters mostly in analog design.
Quick Check
Q: An NMOS has Vth = 0.3 V and V_GS = 0.8 V. Is it in the linear region or saturation at V_DS = 0.2 V? At V_DS = 0.7 V?
Show Answer
Overdrive is 0.5 V. At V_DS = 0.2 V, V_DS is less than 0.5 V, so it is in the linear region. At V_DS = 0.7 V, V_DS exceeds 0.5 V, so it is in saturation.
How Saturation Current Scales With Overdrive
For long-channel transistors, the classic result is that saturation current grows with the square of overdrive. Doubling overdrive gives about four times the current: twice the channel charge, moving about twice as fast.
Modern short-channel transistors do not follow this square law. The lateral electric field along a very short channel is so strong that carriers hit a maximum speed, called velocity saturation. Extra overdrive still adds channel charge, but the carriers cannot go much faster. The result is a relationship much closer to linear.
| Model | Saturation current grows with | Overdrive x2 gives | Applies to |
|---|---|---|---|
| Square law | overdrive2 | ~4× current | Long-channel devices, textbook hand analysis |
| Alpha-power law | overdriveα, α between 1 and 2 | ~2× to 4× current | General empirical fit |
| Short channel (velocity saturated) | overdrive~1 to 1.3 | ~2× to 2.5× current | Modern logic transistors |
Either way, the main levers are the same: more overdrive, more width, or a shorter channel all mean more current. Only the size of the payoff differs.
Where Do These Curves End Up?
Designers rarely use transistor equations directly. Library characterization tools run circuit simulations of every standard cell, using the foundry's detailed transistor models, and store the results as timing tables indexed by input transition time and output load. Static timing analysis then looks up those tables. Every delay number in a timing report ultimately comes from the linear and saturation behaviour described here.
Both Regions in One Logic Transition
Consider an inverter whose output is falling from VDD to 0 because its input has just risen to VDD. The pull-down NMOS has V_GS = VDD for the whole transition, but its V_DS (the output voltage) sweeps from VDD down to 0:
The first part of the transition, which determines most of the 50% delay point, happens with the transistor in saturation, delivering close to its maximum current. The tail of the transition happens in the linear region, where the transistor behaves like a resistor and the output settles gradually. This is why saturation current is the main figure of merit for logic speed, while R_on governs how firmly the output is held at the rail.
Gate delay proportion rule delay proportional to (load capacitance x voltage swing) / drive current load capacitance x2 -> delay x2 drive current x2 -> delay / 2 (wider transistor, or more overdrive)
Where Does R_on Matter Directly?
Power-gating switches are large transistors placed between the power grid and a block that can be shut off. When the block is on, these switches operate deep in the linear region, and their R_on causes a voltage drop that slows the block. Designers size the switch network so that the drop stays within a few percent of VDD, trading area and leakage against performance.
Quick Check
Q: A modern transistor's overdrive is increased from 0.3 V to 0.6 V. Roughly how much does its saturation current increase?
Show Answer
Roughly 2× to 2.5×, because velocity saturation makes the relationship close to linear. The 4× answer applies only to long-channel devices following the square law.
Common Mistakes
Mistake #1: Confusing MOSFET saturation with BJT saturation
In a bipolar transistor, "saturation" means the switch is fully ON with minimum voltage across it. In a MOSFET, that fully-ON, low-voltage condition is the linear region. MOSFET saturation means the current has levelled off and the device acts as a current source. The shared word causes endless confusion.
Mistake #2: Applying the square law to modern transistors
Doubling overdrive gives about 4× current only for long-channel devices. Short-channel transistors are velocity saturated and gain closer to 2×. Using the square law overestimates the benefit of raising VDD or lowering Vth.
Mistake #3: Assuming saturation current is perfectly flat
Channel-length modulation and drain-induced effects make saturation current rise slowly with V_DS. For digital timing this is usually a small correction, but it is why a transistor's output resistance is finite.
Mistake #4: Calling the linear region linear for all V_DS
Current is proportional to V_DS only when V_DS is small compared with the overdrive. Closer to the saturation boundary, the curve bends over. Treating it as a straight line up to V_DSAT overestimates the current.
Practice Exercise
Challenge: Track the Region and Estimate the Speed-Up
An NMOS pull-down has Vth = 0.35 V and VDD = 0.85 V. Its gate is at VDD while the output falls.
- Below what output voltage does the transistor leave saturation and enter the linear region?
- If VDD is raised to 1.10 V (Vth unchanged), by roughly how much does the saturation current rise under the square law, and under a velocity-saturated (near-linear) model?
- Using the delay proportion rule, estimate the delay change for the velocity-saturated case. Ignore the small increase in voltage swing.
Hint
The region boundary is where V_DS equals the overdrive. Compare overdrive before and after the VDD change.
Solution
1. Overdrive = 0.85 - 0.35 = 0.50 V. The NMOS is in saturation while output > 0.50 V, and linear once output drops below 0.50 V. 2. New overdrive = 1.10 - 0.35 = 0.75 V (1.5x the old value) Square law : current ~ 1.5^2 = 2.25x Near-linear model: current ~ 1.5x 3. Delay ~ 1 / current -> roughly 1/1.5 = ~0.67x (about 33% faster). In practice the larger voltage swing takes back a little of that gain.
Summary
In this tutorial, you learned:
- A MOSFET operates in cutoff, linear (triode), or saturation, depending on V_GS and V_DS
- In the linear region, the channel is continuous and the transistor acts as a resistor set by overdrive
- In saturation (V_DS ≥ V_GS - Vth), the channel pinches off near the drain and the current levels off
- Long-channel saturation current grows with overdrive squared; modern short-channel current grows closer to linearly
- A logic transition starts with the driving transistor in saturation and finishes in the linear region
- Gate delay scales with load capacitance and inversely with drive current