A CMOS inverter is built from one PMOS transistor and one NMOS transistor with their gates tied together. When the input is LOW, the PMOS connects the output to VDD; when the input is HIGH, the NMOS connects the output to ground. Because only one transistor conducts in steady state, the inverter draws almost no current except while it is switching.
12 min read | Intermediate Level
What You'll Learn
- How a PMOS pull-up and an NMOS pull-down form an inverter
- What happens inside the inverter during a transition, including short-circuit current
- Why rise and fall times differ, and how transistor sizing balances them
- Where inverters appear in real designs, from logic to clock buffers
The Pull-Up / Pull-Down Structure
Every static CMOS gate has two networks between the power rails:
- A pull-up network of PMOS transistors that can connect the output to VDD.
- A pull-down network of NMOS transistors that can connect the output to GND.
For every input combination, exactly one network conducts. The inverter is the smallest possible case: one transistor in each network.
| Input A | PMOS P1 | NMOS N1 | Output Y | Path |
|---|---|---|---|---|
| 0 | ON | OFF | 1 | Y connected to VDD |
| 1 | OFF | ON | 0 | Y connected to GND |
In both steady states, one transistor is OFF, so there is no direct path from VDD to GND. The only static current is leakage through the OFF transistor. This is the property that let CMOS scale to billions of gates without an enormous standby current.
Where Inverters Appear in Real Designs
A logical inversion becomes an inverter cell from the standard-cell library: one PMOS and one NMOS (2 transistors).
Synthesis often absorbs inversions into neighbouring logic instead of placing a separate inverter. For example, NOT(A·B) maps directly to a single NAND cell, because a NAND gate already has an inverting output. Standalone inverters mostly appear where a signal needs its complement, or as buffers that restore signal strength on long or heavily loaded nets.
Where Are Inverters Used as Buffers?
Clock trees are built almost entirely from inverters and buffers (two inverters in series). Each stage restores a clean, sharp edge before it degrades over a long wire or a large fanout. Clock tree synthesis picks inverter sizes and positions so that the clock reaches thousands of flip-flops at nearly the same time.
Inside a Transition
The input does not jump instantly from 0 to VDD. While it ramps, both transistors pass through intermediate states. Plotting output voltage against input voltage gives the inverter's voltage transfer characteristic (VTC):
Input rising from 0 to VDD, step by step
Vin below Vtn NMOS OFF, PMOS fully ON -> Vout = VDD
Vin just above Vtn NMOS starts to conduct -> Vout begins to drop
Vin near VDD/2 both transistors conducting -> Vout falls steeply
current flows VDD -> GND directly (short-circuit current)
Vin above VDD - |Vtp| PMOS OFF, NMOS fully ON -> Vout = 0
The switching threshold V_M is the input voltage where the output equals the input. It sits where the PMOS pulling up and the NMOS pulling down are equally strong. The steeper the curve around V_M, the better the inverter rejects noise on its input.
While both transistors are partly ON, current flows straight from VDD to GND without charging anything useful. This short-circuit current is one component of switching power. It is usually small - typically under 10% of dynamic power when input and output edges have similar transition times - but it grows when inputs change slowly.
Most of an inverter's switching power does not come from short-circuit current. It comes from charging and discharging the capacitance on the output node every time it toggles.
Quick Check
Q: Why does a slowly rising input make an inverter burn more power, even though the output still switches only once?
Show Answer
The input spends longer in the range between Vtn and VDD - |Vtp|, where both transistors conduct. Short-circuit current flows for that whole time, so a slow input edge wastes more energy. This is why timing tools also limit maximum transition times.
Rise Time, Fall Time, and Sizing
The output falls when the NMOS discharges the load capacitance, and rises when the PMOS charges it. Each edge's speed is set by the current its transistor can deliver:
Edge speed proportion rules
fall time proportional to load capacitance / NMOS current
rise time proportional to load capacitance / PMOS current
holes slower than electrons (planar silicon: ~2-3x)
-> same-width PMOS delivers less current
-> rise time longer than fall time
fix: make the PMOS wider (classic choice W_p = 2 x W_n)
-> rise and fall roughly balanced
-> V_M moves toward VDD/2
Sizing also moves the switching threshold. A stronger PMOS pulls V_M up toward VDD; a stronger NMOS pulls it down toward GND. A balanced inverter with V_M near VDD/2 gives equal noise margins for a noisy 0 and a noisy 1.
| Change | Rise time | Fall time | V_M | Input capacitance |
|---|---|---|---|---|
| Wider PMOS | ↓ Faster | Unchanged | ↑ Higher | ↑ Larger |
| Wider NMOS | Unchanged | ↓ Faster | ↓ Lower | ↑ Larger |
| Both wider (same ratio) | ↓ Faster | ↓ Faster | Unchanged | ↑ Larger |
Where Does Rise/Fall Asymmetry Matter?
Standard-cell timing libraries store separate rise and fall delay tables for every cell arc. Static timing analysis tracks rising and falling edges independently through each path, because a path can be critical for one edge direction and have slack for the other. Clock inverters are often tuned for closely matched edges, since unequal rise and fall times distort the clock's duty cycle as it passes through many stages.
Quick Check
Q: An inverter's rise delay is much larger than its fall delay. Which transistor should you widen, and what happens to the switching threshold?
Show Answer
Widen the PMOS, which charges the output on rising edges. The PMOS gets stronger relative to the NMOS, so the switching threshold V_M moves up toward VDD. The cost is a larger input capacitance for the gate driving this inverter.
Common Mistakes
Mistake #1: Thinking short-circuit current is the main switching power
Short-circuit current flows only while both transistors are partly ON. The dominant switching power is charging and discharging the output load capacitance. With reasonable edge rates, short-circuit current is a small fraction of the total.
Mistake #2: Assuming equal-size transistors give equal rise and fall
In planar silicon, holes are 2 to 3 times slower than electrons, so a PMOS the same width as the NMOS makes the rising edge noticeably slower. Always check the library's separate rise and fall numbers rather than assuming symmetry.
Mistake #3: Confusing the switching threshold with the transistor threshold voltage
V_M is a property of the whole inverter and usually sits near VDD/2. Vtn and |Vtp| are properties of individual transistors, typically a few hundred millivolts. They are different quantities used for different purposes.
Mistake #4: Adding inverter pairs "for safety" in the logic
Writing a double inversion or a chain of inverters in the logic description does not create deliberate delay or buffering; synthesis simply optimizes them away. Buffering is inserted by the implementation tools based on load and timing, and deliberate delay elements need tool-specific handling.
Practice Exercise
Challenge: Balance an Inverter
An inverter has W_n = 100 nm and W_p = 100 nm. In this process, a PMOS delivers 40% of the current of an NMOS of the same width.
- How much longer is the rise time than the fall time?
- What PMOS width gives equal rise and fall times?
- After resizing, by what factor has the inverter's input capacitance changed?
Hint
Edge time is proportional to load divided by current. Input capacitance is proportional to total transistor width.
Solution
1. PMOS current = 0.4 x NMOS current at equal width rise time / fall time = 1 / 0.4 = 2.5x longer 2. Need PMOS current = NMOS current W_p = 100 nm / 0.4 = 250 nm 3. Before: 100 + 100 = 200 nm of gate width After: 100 + 250 = 350 nm of gate width Input capacitance grows by 350 / 200 = 1.75x
Balanced edges put a heavier load on the stage driving this inverter. Many libraries use a ratio somewhat below full balance for this reason.
Summary
In this tutorial, you learned:
- A CMOS inverter is one PMOS pull-up and one NMOS pull-down with a shared gate
- In steady state exactly one transistor conducts, so static current is only leakage
- During a transition both transistors briefly conduct, causing a small short-circuit current
- The switching threshold V_M is where pull-up and pull-down strengths balance, usually near VDD/2
- Slower holes make the rising edge slower unless the PMOS is made wider
- An inversion becomes an INV cell, but tools often absorb inversions into NAND, NOR, and complex cells
