Process Corners in Silicon: Skew Lots

A skew lot is a batch of wafers that the fab processes on purpose to land at the edges of the process window, making transistors faster or slower than normal. Testing parts from these wafers shows how the design behaves at the process corners it was signed off at, long before natural variation would produce such parts in volume.

Without skew lots, validation would only see the typical silicon that the first wafers happen to produce. This article explains how corner wafers are made, what each corner is used to check, and how teams know where a given part sits in the process.

6 min read | Intermediate

What You'll Learn

• Explain what a skew lot is and why it is ordered
• Name the process corners and what each one stresses
• Use process monitors to place a part in the process spread
• Plan which tests run on which corner parts

Why Corners Matter

Timing sign-off checks the design at process corners: slow transistors for setup, fast transistors for hold and leakage, and mixed corners where NMOS and PMOS differ. Those corners are a promise about every part that will ever ship.

First silicon usually comes out near the typical point. A design that only works on typical parts will fail later, when production drifts to a corner. Skew lots let validation test the corners early and on purpose.

How a Skew Lot Is Made

The fab splits a lot into groups and changes a few process steps for each group, such as channel implants or gate length, so that transistor speed moves in a controlled direction. The groups are tracked separately through the rest of the flow.

The usual targets are named by NMOS speed then PMOS speed:

• TT: typical NMOS, typical PMOS.
• FF and SS: both fast, or both slow.
• FS and SF: one fast and one slow, the mixed corners.

Real skew wafers rarely land exactly on the corner. They land near it, and some spread remains within each wafer.

What Each Corner Checks

• SS parts set the speed limit. Shmoos at high temperature and low voltage show whether the slowest silicon still meets the frequency target.
• FF parts set the power and thermal limit. They leak the most and run hottest. They also stress hold timing, because data arrives early.
• FS and SF parts stress circuits that depend on a balance between NMOS and PMOS strength: SRAM cells and their write margin, sense amplifiers, keepers on dynamic nodes, and level shifters.

Analog blocks are checked at every corner, because trim range and bias currents have to cover all of them, as in PLLs and Analog Blocks on Silicon.

Knowing Where a Part Sits

Each part carries process monitors: ring oscillators built from standard cells, and simple transistor test structures. Their frequency or current shows how fast that piece of silicon is, independent of the design's logic.

Plotting a measured quantity such as maximum frequency against the ring oscillator frequency shows whether the design tracks the process. Parts that fall off the trend are interesting, because something other than transistor speed is limiting them.

In Practice

Skew lots are expensive and slow, so they are planned early, often started together with the first engineering wafers. Teams decide in advance how many parts from each corner go to each lab: speed and power characterization, I/O, analog, and reliability. The results feed directly into Fmax, Speed Bins and Binning and into the guard bands of production test.

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