Transistors and wires slowly change as a chip is used. Threshold voltages drift up, drive currents fall, gate oxides leak more, and metal atoms move in high-current wires.
Over years these effects make paths slower until, without enough margin, the chip fails. This is aging, or wear-out. This article describes the main aging mechanisms, what makes each worse, and how validation measures aging on real silicon.
7 min read | Advanced
What You'll Learn
- Explain NBTI, hot carriers, oxide breakdown and electromigration
- Identify the conditions that accelerate each mechanism
- Describe how aging is measured on silicon
- Explain how aging is covered by guard bands
The Mechanisms
NBTI
Negative bias temperature instability affects pMOS transistors held on, with the gate low and the source high, especially at high temperature. Traps form at the oxide interface and the threshold voltage rises, reducing drive current.
The shift grows roughly with the fourth root of time: fast at first, then slowly. In many nanometer processes NBTI is the most important oxide wear-out mechanism.
Hot Carriers
When a transistor switches with a large drain voltage, a few high-energy carriers are injected into the gate oxide and trapped. In nMOS transistors this reduces current. It is worst for gates with fast-rising inputs driving heavy loads, and at high supply voltage.
Hot carriers can also unbalance matched circuits, such as sense amplifiers, if their two halves age differently.
Oxide Breakdown
Under a strong electric field the gate leakage slowly rises, and eventually the oxide can break down and short the gate. A common guideline for a ten-year life at 125 °C is to keep the oxide field below about 0.7 V/nm. Supply overshoots and noise make it worse.
Electromigration
High current density in a wire pushes metal atoms along with the electrons, forming voids that raise resistance and eventually open the wire. It mostly affects wires with current in one direction, such as power grids and the wires connecting transistors to supplies.
Lifetime falls with roughly the square of current density and drops sharply with temperature. Copper tolerates much higher current densities than aluminium.
Quick Check
Q: Which mechanism mainly threatens a pMOS transistor in a clock-gated block that sits with its input low for long periods at high temperature?
Show Answer
NBTI. A pMOS with its gate low and source high is under negative bias, and high temperature speeds trap formation. Its threshold voltage rises, slowing any path through it when the block becomes active again.
How Aging Shows Up
At circuit level, aging slows paths. A part that reaches 2.0 GHz new might reach a few percent less after years of use. Matched circuits such as memory cells and sense amplifiers can also lose margin as their transistors age unevenly.
Because NBTI is fast at first, burn-in locks in a large part of the shift before shipping, which lets production test measure parts closer to their aged state.
Measuring Aging on Silicon
- Measure fresh parts: Fmax, minimum voltage, ring oscillator frequency, leakage.
- Stress them at raised voltage and temperature for set intervals.
- Measure again after each interval.
- Fit the degradation against stress time and extrapolate to the product lifetime at normal conditions.
Many chips also include aging monitors: pairs of ring oscillators, one stressed during operation and one kept idle, whose frequency difference shows how much the silicon has aged in the field.
Quick Check
Q: After stress equivalent to ten years, Fmax drops 3 %. The production guard band reserves 2 % for aging. What is the risk?
Show Answer
Parts tested with just enough margin may fail late in life, because aging takes 1 % more than reserved. The guard band must grow, or the design or voltage must reduce aging.
In Practice
Aging data feeds the guard bands in Margins and Guard Bands, the maximum operating voltage of the product, and electromigration and current limits used in the next design. Some products compensate in the field, raising voltage slightly over time when aging monitors show slowing.
Common Mistakes
Mistake #1: Ignoring aging in the guard band
Parts that pass new may fail after years. Reserve margin for measured aging.
Mistake #2: Assuming all paths age equally
Aging depends on how long each transistor spends under stress. Idle or always-on circuits can age differently.
Mistake #3: Overlooking electromigration in signal-to-supply connections
Wires that carry current in one direction need density limits too.
Practice Exercise
Challenge: Fourth-Root Growth
A threshold shift follows ΔVt proportional to t0.25. After 1 year the shift is 20 mV. Estimate the shift after 10 years and after 16 years.
Hint
Multiply by (t / 1 year)0.25.
Solution
100.25 is about 1.78, so about 36 mV after 10 years. 160.25 = 2, so 40 mV after 16 years. Most of the shift happens early, which is why burn-in can lock in a large part of it.
Summary
- NBTI raises pMOS thresholds under negative bias and heat; it grows with about the fourth root of time.
- Hot carriers degrade nMOS transistors with fast inputs and heavy loads.
- Oxide breakdown and electromigration depend strongly on field, current density and temperature.
- Aging is measured by stressing parts and re-measuring, and is covered by guard bands.
