A speedpath is a timing path that fails first on silicon as the clock frequency rises. Finding speedpaths tells the team what limits Fmax, whether timing sign-off missed something, and which paths a metal fix or the next stepping should speed up. This article explains how a speedpath shows up, how teams find the failing cycle and path, and the options for fixing it.
7 min read | Advanced
What You'll Learn
- Recognize a speedpath failure on a shmoo
- Explain how clock stretching finds the failing cycle
- Go from the failing cycle to the failing path
- Compare the options for fixing a speedpath
Recognizing a Speedpath
A speedpath failure follows the normal shmoo pattern of Shmoo Plots: the test passes below a frequency that rises with voltage, and fails above it. The failure is usually deterministic for a given test, voltage and temperature, which makes it easier to debug than noise problems. The question is which path, out of millions, fails first, and in which cycle of the test.
Finding the Failing Cycle
Many chips can lengthen a single chosen clock cycle, called clock stretching, while every other cycle runs at full speed. The test runs at a failing frequency, and one cycle at a time is stretched.
If stretching cycle N makes the test pass, a path that ends in cycle N is too slow. Sweeping N, often by bisection over the cycles of a short test, finds the failing cycle. Some designs can also shorten a single cycle, which finds paths that are close to failing.
Quick Check
Q: A test fails at 2.2 GHz. Stretching cycle 5,120 alone makes it pass; stretching any other cycle does not. What does this show?
Show Answer
The path that fails at 2.2 GHz is captured at the end of cycle 5,120. The next step is to look at which flops capture data in that cycle and which of their paths were active, to identify the specific path.
From Cycle to Path
A state dump just after the failing cycle, compared with simulation, shows which flip-flops captured wrong values. Those are the endpoints of the failing path.
Timing analysis lists the paths ending there, and simulation of that cycle shows which of them were actually switching. The intersection usually leaves a few candidate paths, which are compared with their predicted slack. Techniques from Physical Failure Analysis, such as laser voltage probing, can measure the path timing directly when the candidates remain ambiguous.
Fixing a Speedpath
- Clock adjustment: some chips have programmable clock delays, set by fuses, that give a slow path a little more time by borrowing from the next stage.
- Metal fix: resize or re-buffer cells, using spare cells and changing only metal layers, as in Metal Fix or Full Respin.
- Redesign: restructure the logic in a full new stepping.
Fixing one speedpath only raises Fmax until the next path fails. Teams usually collect a list of speedpaths and fix many at once, until a target frequency is reached.
Quick Check
Q: Fixing the top speedpath raised Fmax by only 1 %. Why might that be?
Show Answer
The next slowest path was only about 1 % faster, so it now limits Fmax. Speedpaths often come in groups with similar delay, which is why teams find and fix many at once.
In Practice
Speedpath debug runs throughout the program, on parts from skew lots and at several voltages and temperatures, since different paths can be limiting at different conditions. The results also feed silicon correlation: each speedpath that was not near the top of the timing report reveals a gap in the sign-off flow.
Common Mistakes
Mistake #1: Fixing only the first speedpath
The next path usually limits almost as much. Collect and fix a group.
Mistake #2: Finding speedpaths at one voltage only
The limiting path can change with voltage and temperature. Check several conditions.
Mistake #3: Assuming the timing report's top path is the silicon speedpath
Silicon often disagrees. Find the real failing path.
Practice Exercise
Challenge: Plan the Fixes
A part reaches 1.9 GHz. The five slowest silicon paths would allow 1.90, 1.92, 1.95, 1.96 and 2.05 GHz if they were the only limit.
The target is 2.0 GHz. Which paths must be fixed, and what Fmax results if only the first two are fixed?
Hint
Fmax is set by the slowest remaining path.
Solution
Every path below 2.0 GHz must be fixed: the first four. Fixing only two leaves the 1.95 GHz path limiting, so Fmax rises from 1.90 to 1.95 GHz. Reaching 2.0 GHz needs four fixes, and some margin above the fourth path's new speed.
Summary
- A speedpath is the path that fails first as frequency rises.
- Clock stretching of single cycles finds the failing cycle.
- State dumps, timing reports and simulation identify the failing path.
- Fixes range from clock adjustment to metal fixes to redesign; many paths are fixed together.
