Tapeout Readiness and SoC Sign-Off

Tapeout readiness is the judgement that a chip's design is complete and correct enough to send for manufacture. The name comes from the days when the final layout was written to magnetic tape and delivered to the factory. Today the files go over a network, but the step is just as final: after tapeout, the masks are made and wafers start through a process that takes months and costs millions, and any bug left in the design is in every chip. This article explains what must be true before tapeout, how teams check each part, how they handle the problems that remain, and what happens when the first chips come back.

12 min read | Intermediate

What You'll Learn

• Explain why tapeout is such a costly, final step
• List the sign-off checks a chip must pass before tapeout
• Describe how teams track readiness and handle waivers
• Describe what happens after tapeout, from masks to bring-up

Why Tapeout Is Final

Once a design is taped out, the factory makes a set of masks, one for each layer of the chip, and starts wafers through dozens of steps for each layer. For an advanced process, a full mask set can cost many millions, and the first chips arrive two to four months later. If a serious bug is found in the first silicon, fixing it means changing the design, making at least some new masks and waiting months again. A product that misses its launch because of a respin can lose more in sales than the chip cost to design.

The pressure therefore runs in two directions. Every week of delay before tapeout costs schedule, but every bug that escapes costs much more. Tapeout readiness is the process that balances them: a clear list of what must be true, evidence for each item, and an explicit decision about anything that falls short.

The Sign-Off Areas

Readiness covers several areas, each with its own owner and criteria.

The Physical Sign-Off Checklist in the Physical Design tutorial covers the physical checks in detail. This article looks at the whole chip.

Functional Sign-Off

Functional sign-off relies on the verification plan described in SoC-Level Verification Strategy. Every feature in the plan must have its tests written and passing, and coverage must reach its goals. Some coverage holes are acceptable, for example code for a mode the product will never use, but each one is reviewed and its reason recorded. The bug rate must have fallen, and every known bug is either fixed or has a documented decision, such as a software workaround.

Equivalence checking connects function to the physical design. Verification ran on the RTL, but the chip is built from the netlist after synthesis, test insertion, clock tree building and many late fixes. A formal equivalence check proves that the final netlist computes the same function as the RTL that was verified, so that no step on the way broke it.

Timing and Physical Sign-Off

Timing sign-off runs static timing analysis on the final layout, with the extracted wire resistance and capacitance, at every combination of process corner, voltage, temperature and operating mode the chip will use. Every path must meet its setup and hold requirements with margin. DVFS operating points, as Dynamic Voltage and Frequency Scaling explains, multiply the number of modes. Multi-Corner Sign-Off With SPEF in the Static Timing Analysis tutorial covers the method.

Physical sign-off checks the layout itself. Design rule checks (DRC) confirm that every shape obeys the factory's rules for width, spacing and density. Layout versus schematic (LVS) confirms that the layout's transistors and wires form exactly the circuit in the netlist. Power integrity checks confirm that the supply holds up under the worst switching activity and that no wire carries more current than it can for the chip's lifetime. A chip that fails any of these may not work, or may not be manufacturable at all.

Tracking Readiness

A large chip has hundreds of readiness items, owned by different teams. Projects track them in a single list, reviewed often in the last months, with each item's status, owner and evidence: the report, the regression result, the review record. A common approach sets intermediate milestones before the final tapeout, such as a freeze of the RTL features, then of the RTL itself, then of the netlist, each with its own criteria, so that problems surface early rather than all at once in the final week.

The final step is a tapeout review: the leads of each area present their evidence, the open issues and the risks, and the project decides to tape out or not. The decision is recorded, together with any condition, such as a known bug with a workaround. If the answer is to wait, the review names what must change and who will check it, and the review meets again once it has.

Waivers

Almost no chip tapes out with every check perfectly clean. A waiver is a documented decision to accept a violation: a DRC error in a test structure that the factory confirmed is harmless, a clock crossing that isn't synchronized because the signal is static once configured, a coverage hole in an unused mode. Each waiver records what the violation is, why it is safe, who approved it, and what would make it unsafe.

Waivers are necessary but dangerous. A waiver written early in the project may no longer be true after a later change, and a long list of waivers can hide a real problem among the harmless ones. Good practice reviews every waiver again before tapeout, and makes the tools match waivers precisely, so that a new violation in the same area isn't silently covered by an old waiver.

Leaving Room to Fix

Teams know that some bugs will escape, so they plan for fixes that don't need a full respin. Spare cells, unused gates scattered across the layout, can be connected by changing only a few metal layers, so a small logic fix needs new masks for those layers only, which is much cheaper and faster. This is a metal ECO, an engineering change order, and ECOs After Routing in the Physical Design tutorial covers how one is made.

Other fixes rely on software. Chicken bits, configuration bits that turn off a new feature or switch to a slower but safer behaviour, let software avoid a bug in a new block. Patchable boot code, where the ROM checks for patches in OTP or flash before running its main code, allows boot bugs to be worked around. Every one of these must be planned and verified before tapeout, since adding them afterwards is impossible.

What Goes Out, and What Stays

The delivery to the factory is the final layout, usually in the GDSII or OASIS format, with a few files describing the layers, the fill and any special processing. The factory runs its own checks on the files and may send back questions before it accepts them. GDSII Out and Tapeout covers the physical side of this step.

Just as important is what the team keeps. Every file that produced the taped-out layout is archived and tagged: the RTL, the constraints, the scripts, the tool versions, the netlists and all the sign-off reports. When a bug appears in silicon months later, the team must be able to rerun the exact simulation and timing analysis that matched the chip. A metal ECO must start from the exact database that was taped out, not from a later version with other changes in it.

The documents that go to customers are also frozen at tapeout: the datasheet's register descriptions, the errata list of known bugs and workarounds, and the safety manual for chips sold into safety-related products, as Safety and Reliability describes. They are updated as silicon validation confirms or corrects them.

After Tapeout

The factory checks the files, makes the masks and starts the wafers. While they are in the factory, the team prepares for bring-up: the test programs for the tester, the evaluation boards, the software, and the plans for which tests to run first. Who Does What After Tapeout describes the steps from the factory side.

When the first chips arrive, they are tested on the tester, then mounted on boards. Bring-up starts with the simplest checks: power and clocks, then JTAG access, then the boot ROM, then the first C tests reused from simulation, and finally the operating system. Silicon validation then tests the chip thoroughly at every voltage and temperature it must support, measures its performance and power against the models, and characterizes its operating points. Bugs found are triaged: worked around in software, fixed with a metal ECO, or fixed in a later full revision of the chip.

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