Choosing IP is the decision, for each block of an SoC, whether to buy it from a vendor, reuse a design the company already has, or build it new. IP, short for intellectual property, is the industry's word for a reusable block design. A modern SoC contains dozens to hundreds of such blocks, and almost none of them are designed from scratch for that chip. Getting these choices right decides much of a project's cost, schedule and risk. This article explains the three options, what an IP delivery contains, how licensing works, how to judge the quality of a block, and how teams decide.
12 min read | Beginner
What You'll Learn
- Compare buying, reusing and building a block by cost, risk and control
- List what a complete IP delivery contains
- Explain common licensing models and what they cost
- Evaluate the quality and fit of a block before committing to it
Why Not Design Everything?
A phone chip may contain processor cores, a GPU, video and image engines, a modem, memory controllers, USB, PCIe, display and camera interfaces, dozens of small peripherals, and the analog circuits that drive the pins. No company could design all of that new for each chip, or verify it in time. And most of it is not what makes a product sell: a USB controller has to work, but nobody buys a phone for its USB controller.
So SoC design is mostly an exercise in assembling blocks, and What Is in an SoC describes the kinds of block involved. For each one, a team chooses among three sources.
The Three Options
Buy
A third-party IP vendor sells designs that many customers use. Processor cores, interface controllers with their PHYs (the analog circuits at the pins), memory controllers and standard interconnects are commonly bought. The design has usually been proven in silicon many times, it comes with documentation and support, and it can be integrated in weeks rather than built in years. Standard interfaces such as USB, PCIe or DDR are particularly worth buying, because their specifications run to thousands of pages, and compliance testing is hard.
The costs are money, and control. A licence fee is paid up front, and often a royalty per chip sold. The vendor's design may be larger or more general than needed. You can only change what the licence allows, and a bug in the vendor's block depends on the vendor to fix it.
Reuse
Companies keep libraries of their own blocks from earlier chips. Reusing one costs no fee, its quality is known from silicon, and the team understands it. But it may not fit the new product perfectly: an older bus interface, a different process, missing features. Reuse often means adapting a block, which takes real effort, and the original authors may have moved on. Good reuse depends on good documentation and clean interfaces, which is one reason companies invest in internal standards.
Build
Designing a block new gives an exact fit and full ownership. It is the right choice when the block is what makes the product better than its competitors, such as a special accelerator or a custom processor, or when nothing suitable exists. It is also the most expensive and risky option: design, verification, and often a test chip, all on the project's critical path.
The usual rule is to build what differentiates, and buy or reuse the rest. A company making an image processor builds the image pipeline and buys the USB.
Quick Check
Q: A startup building a machine learning accelerator chip needs a PCIe interface, a RISC-V control core and its matrix engine. Which would it most likely buy, and which build?
Show Answer
Buy the PCIe controller and PHY, which are complex standard blocks needing compliance, and buy or license the control core, which is not the product's value. Build the matrix engine, which is what the company sells.
What an IP Delivery Contains
A block is far more than its RTL. A complete delivery usually includes:
| Item | What it is for |
|---|---|
| RTL, or a netlist for hard IP | the design itself |
| Integration guide and register map | how to connect it and program it |
| Configuration options | parameters such as FIFO depths, bus widths, optional features |
| Test environment and test suite, or verification IP | proof that it works, and a way to check your integration |
| Timing constraints (SDC) | so synthesis and timing analysis treat it correctly |
| Synthesis scripts and area and power data | to plan the floorplan and the power budget |
| Software drivers and examples | so firmware can use it on day one |
| Errata list and release notes | known problems and what changed |
Soft IP is delivered as RTL, so it can be built in any process and configured. Hard IP is delivered as a finished layout for one specific process, usually because it is analog, such as a PHY or a PLL, or because it has been tuned for speed. Memory blocks are often generated by a memory compiler for the chosen process, as Memories in a System describes.
Licensing
IP is licensed in several ways, and the terms often matter as much as the technical choice:
- A per-project licence covers one chip design. Another chip needs another licence.
- A multi-use or perpetual licence covers several designs, for a higher fee.
- A royalty is paid per unit shipped, often a small percentage of the chip price or a few cents per chip. It makes the block cheap up front and expensive at high volume.
- An architecture licence, offered by some processor vendors, allows a company to design its own core that implements the vendor's instruction set.
- Open-source IP, such as many RISC-V cores and peripherals, has no fee, but usually no warranty or support either, unless a company provides it as a service.
A simple calculation shows why royalties matter. With an assumed fee of 500,000 dollars and a royalty of 5 cents per chip, a product selling 2 million units pays 600,000 dollars in total, and one selling 100 million units pays 5.5 million. These numbers are assumptions for this example. The same block may be cheap for a niche product and very expensive for a high-volume one, so volume estimates go into the choice.
RISC-V has changed this market. Because the instruction set is free to use, companies can build their own cores, use open-source ones, or buy from many competing vendors, rather than having one supplier for each ISA. What an ISA Defines explains why an open ISA makes that possible.
Where Does This Matter?
An IP choice made early can lock a product in for years. If a team picks an interconnect from one vendor, its other blocks must speak that protocol. If it picks a memory PHY qualified only in one foundry's process, the whole chip is tied to that foundry. For that reason, large companies have teams that evaluate IP, negotiate licences, and keep a list of approved suppliers, and the choice is reviewed by architects, legal teams and purchasing together.
Judging Quality
Before committing, a team checks a candidate block carefully. Useful questions include:
- Silicon history. In how many chips, in which processes, has this exact version shipped?
- Verification. What coverage was reached? Is there verification IP that can check our integration?
- Configurability. Can it be set up to our needs, and are the configurations we need actually tested?
- PPA. What are its area, power and frequency in our process and library?
- Interfaces. Does it speak our interconnect protocol and clocking scheme, or does it need bridges?
- Deliverables. Are all the items in the table above present and up to date?
- Support. How fast does the vendor fix bugs? Is there an errata list, and what is on it?
- Security and safety. For products that need it, are there safety documents and security reviews?
Many teams run a small trial integration first: synthesize the block in their own flow, connect it to a test top level, and run the vendor's tests and a few of their own. A few weeks of trial can save months of trouble later.
Hidden Costs
The list price is not the full cost. Integration takes engineering time: wrappers to adapt the interfaces, clock and reset connections, register maps in the spec, drivers in software, and tests at the system level. A block with a non-standard interface can cost more to integrate than one that is more expensive but plugs straight in. Every block also adds verification at the SoC level, as Top-Level Integration and Connectivity Checks describes.
Quick Check
Q: Block A costs 200,000 dollars and needs a bus bridge that will take 3 engineer-months to build and verify. Block B costs 280,000 dollars and plugs straight in. An engineer-month costs 20,000 dollars, all included. Which is cheaper?
Show Answer
A: 200,000 + 3 x 20,000 = 260,000 dollars. B: 280,000. A is slightly cheaper in money, but the bridge adds risk and schedule. Many teams would choose B for the lower risk, especially if the schedule is tight.
Making the Decision
A decision for each major block can be laid out in a simple table: candidate sources, costs, time to integrate, risks, and fit with the architecture. Architects score each option, and the team agrees on the result in a review. The decision then goes into the system architecture spec, with the reasons, so that it can be revisited if the facts change.
A few situations push the answer strongly one way:
- The block is a complex standard with compliance tests: buy.
- The block is the product's main value: build.
- A proven internal block fits with small changes: reuse.
- The schedule is very tight: buy or reuse, even at a higher cost.
- Volumes are huge and royalties would be large: consider building or an open-source option.
Thinking Beyond One Chip
An IP choice outlives the chip it was made for. Software, drivers and tests built around a block are reused in the next product, so changing vendors later has a real cost. Teams therefore ask about the vendor's roadmap: will the block be available in the next process node, and will the vendor still support it in five years? For products with long lives, such as cars or industrial equipment, a chip may need to be made for ten years or more, so the IP must stay available and supported for that long. Some companies insist on a second source, or on access to the source code if the vendor disappears, through an arrangement called an escrow agreement.
Common Mistakes
Mistake #1: Comparing only the licence price
Integration, verification, royalties and support all add to the cost. Compare the total cost and the risk to the schedule, not the quote.
Mistake #2: Using an untested configuration
A configurable block may only have been verified in a few settings. Choosing an unusual combination of parameters can mean being the first user of that configuration in silicon. Ask which configurations are proven.
Mistake #3: Building what could be bought
Teams sometimes build a standard block out of pride or caution, and then spend a year on something that gives the product no advantage. Save the design effort for what makes the product different.
Practice Exercise
Challenge: Royalty or Fee?
A team can license a processor core in two ways. These numbers are assumptions for this exercise. Option 1: 1,000,000 dollars up front, no royalty. Option 2: 200,000 dollars up front plus 10 cents per chip. (a) At what volume do the two cost the same? (b) Which is cheaper at 3 million units, and by how much? (c) The product has an uncertain market: it might sell 2 million or 20 million units. Which option limits the risk, and why?
Hint
Set the two total costs equal and solve for the number of chips.
Solution
(a) 1,000,000 = 200,000 + 0.10 N, so N = 8 million units. (b) Option 2 at 3 million: 200,000 + 300,000 = 500,000 dollars, half the cost of option 1. (c) Option 2 costs little if sales are low, and costs 2.2 million at 20 million units, which the company could afford because the product succeeded. Option 1 costs 1 million whatever happens. A royalty shares the risk with the vendor, which is attractive when sales are uncertain.
Summary
- SoCs are mostly assembled from IP blocks, bought, reused or built.
- Build what makes the product different, and buy or reuse the standard blocks.
- A delivery includes RTL, documents, configuration, verification material, constraints, drivers and errata.
- Licences may be per project, multi-use, royalty-based, architecture licences or open source; volume changes which is cheaper.
- Judge quality by silicon history, verification, fit, PPA and support, and count the hidden cost of integration.