Polling, Interrupts and DMA

Devices are slow compared with processors. A UART needs hundreds of clock cycles to send one byte, a sensor may produce a reading once a second, and a network packet can arrive at any moment. A system has three ways to deal with that. With polling, the processor checks the device again and again. With interrupts, the device signals the processor when it needs attention. With DMA, a separate engine moves the data and the processor only hears about the result. This article explains all three, shows what polling costs on a small SoC, describes step by step what happens when an interrupt arrives, and shows how to choose.

13 min read | Beginner

What You'll Learn

• Explain polling, interrupts and DMA and what each costs the processor
• Calculate how much of a program's time goes to polling from its instruction counts
• Describe step by step what a RISC-V processor does when an interrupt arrives
• Choose between the three methods for a given device and data rate

The Problem: Devices Are Slow

Take a UART that sends each byte as 10 bits, with each bit lasting 16 clock cycles, so one byte takes 160 cycles. In that time the processor could execute well over a hundred instructions. The UART has an 8-byte FIFO (first in, first out buffer) that holds bytes waiting to be sent, so the processor can hand over a few bytes at once, but once the FIFO is full, it has to wait for room.

The question every system must answer is: what does the processor do while a device is not ready, and how does it learn that the device is ready again? There are three answers, shown side by side below:

Polling

Polling means reading the device's status register in a loop until the device reports it is ready, then doing the transfer. A simple UART driver does exactly this before every byte:

while (UART_STATUS & 1)            /* bit 0: FIFO full */
    ;
UART_TXDATA = (u32)c;

The compiler turns the loop into three instructions: a load of STATUS, an AND that keeps bit 0, and a branch back while the bit is 1. Memory-Mapped I/O and Registers explains the registers and why STATUS must be declared volatile.

Polling is the simplest method, needs no extra hardware, and reacts fastest once the device is ready, because the processor is already looking. Its cost is that the processor can do nothing else while it waits.

Measuring the Cost

In one test, a small program sent 256 bytes over the UART by polling, generating each byte and updating a checksum as it went. It was run at two UART speeds, set by the DIV register (clock cycles per bit): DIV = 16, and four times faster at DIV = 4. At the slow speed the program read the status register about 13 times per byte. At the fast speed it read it about twice per byte, and the whole run took about a quarter of the time.

Each status read is one pass through the three-instruction loop, so the polling instructions are easy to count. Taking them away from the total leaves the real work, and that came out exactly the same at both speeds. The program did identical work; the only difference is how long it spent asking the UART whether it was ready. At the slow speed, 72 percent of all instructions executed were polling. At the fast speed it was 28 percent.

And it is not only instructions: every status read is a bus access that costs 6 cycles, which is why the core spent over 40 percent of the slow run waiting on the bus. In practice the whole run was spent sending 256 bytes, and nothing else could happen in the meantime.

Interrupts

An interrupt turns the question around: instead of the processor asking the device, the device tells the processor. The device has an output wire, its interrupt request line, which it drives high when it needs attention, for example when its FIFO has room or new data has arrived. A timer is a simple example: its irq output is high while its cycle counter MTIME is greater than or equal to the compare value CMP, so software can ask to be woken at a chosen time.

What Happens When an Interrupt Arrives

The processor checks the interrupt line between instructions. In a RISC-V processor running in machine mode, the most basic privilege level, this is what happens when an enabled interrupt is pending:

1. The processor finishes the current instruction and does not start the next one.
2. It saves the address of the instruction it would have run next in a special register, mepc (machine exception PC), records the reason in mcause, and disables further interrupts.
3. It jumps to the address held in mtvec (machine trap vector), where software has placed the interrupt handler, also called the interrupt service routine.
4. The handler saves the general-purpose registers it will use on the stack, serves the device (for example, writes the next bytes into the UART FIFO, which makes the device lower its request), and restores the registers.
5. The handler ends with the instruction mret, which jumps back to the address in mepc and enables interrupts again. The interrupted program continues as if nothing had happened.

The special registers are CSRs, control and status registers, which hold the processor's own settings rather than program data.

The benefit is that the processor runs other work, or sleeps, between interrupts. The price is the overhead of each interrupt: emptying the pipeline, the jump, saving and restoring registers, and the return. That typically costs tens of cycles on a small core before the handler does any useful work. The time from the device's request until the handler starts is the interrupt latency, and real-time systems specify a maximum for it.

For the UART, an interrupt each time the FIFO becomes empty would let the handler write 8 bytes per interrupt: 256 bytes would need 256 / 8 = 32 interrupts, and between them the processor would be free.

Enabling, Prioritizing and Sleeping

A processor does not take every interrupt that arrives. Each source has an enable bit, and there is a global enable that switches all of them on or off. In a RISC-V processor the mie register (machine interrupt enable) holds one bit per source: bit 3 for software interrupts, bit 7 for the timer, bit 11 for external interrupts from devices. The matching bits of mip (machine interrupt pending) show which sources are requesting, and the MIE bit of mstatus is the global switch. An interrupt is taken only when its pending bit, its enable bit and the global enable are all 1. That is how software can set up a handler first and only then let interrupts in, and how it can briefly block them while it changes data that a handler also uses.

When several sources request at once, the processor needs a rule for which one to serve first: a priority. A fixed order is common, with an interrupt controller in front of the processor deciding among many devices. Some systems also allow nesting: a high-priority interrupt may interrupt the handler of a lower-priority one, which keeps the latency of urgent events short at the cost of more complex software.

Interrupts also let a processor sleep. RISC-V has the instruction wfi (wait for interrupt): the processor stops executing and can stop its clock until an enabled interrupt becomes pending. An idle loop built on wfi instead of polling uses a small fraction of the power. A typical low-power program sets the timer's compare register to the next deadline, executes wfi, does its work when the timer wakes it, and goes back to sleep.

DMA: Let Another Block Move the Data

For large amounts of data, even one interrupt per few bytes is too much. DMA, direct memory access, hands the whole transfer to a separate block, the DMA engine. It is a bus manager like the processor: it can read and write memory and device registers by itself.

The processor programs it through its registers: the source address (for example a buffer in SRAM), the destination (the UART's TXDATA register), the number of bytes, and a start bit. The DMA engine then moves the data, checking the device's readiness signals itself, and raises one interrupt when it has finished. For the 256-byte stream that would be one setup, one interrupt and, between them, a processor free for other work.

DMA has costs too. The engine is extra hardware. It shares the interconnect with the processor, so the two sometimes compete for the same bus or memory and one has to wait. And software must make sure the processor does not change a buffer while the DMA engine is still reading it. DMA Engines goes further into how such an engine works.

Choosing Between Them

Real systems combine them. A network interface uses DMA for the packet data and an interrupt to say that packets have arrived; boot code polls because it has nothing else to do yet; a driver may poll for a few microseconds before falling back to an interrupt, because for very short waits the interrupt overhead costs more than it saves.

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