Design for Test at SoC Level

Design for test, DFT, is the set of structures added to a chip so that each manufactured part can be checked quickly for defects. Manufacturing is never perfect: a speck of dust or a weak via can break a wire or short two together, and some fraction of every wafer is faulty. A chip with billions of transistors can't be tested by running programs on it and hoping, so designers build test access into the hardware. This article explains why test is needed, how scan chains and test patterns find faults in logic, how memories test themselves, how a chip is reached from the test equipment through JTAG, and how test decisions are made for a whole SoC.

12 min read | Intermediate

What You'll Learn

• Explain why manufactured chips need structured test
• Describe scan chains, fault models and test coverage
• Explain memory built-in self-test and repair
• Describe JTAG and test planning across an SoC

Why Test Is Needed

Verification checks that the design is right; manufacturing test checks that each chip was built as designed. Every chip from the wafer is tested, and faulty ones are thrown away before they are packaged or shipped. The yield is the fraction of chips that pass. For a large chip on a new process, yield may start well below one half and improve as the process matures.

Test time costs money: the test equipment, called automatic test equipment or ATE, is expensive, and every second a chip spends on it adds to the chip's cost. A test must therefore find nearly every defect in as little time as possible. Shipping a faulty chip is far worse than the test cost: customers measure quality in defective parts per million, and car makers ask for numbers close to zero.

Fault Models

Real defects are physical and varied, so tests are written against simple fault models that represent them. The most common is the stuck-at model: any one wire in the logic may be stuck at 0 or stuck at 1. A test pattern detects a stuck-at fault if, with the fault present, some output of the chip has a different value than without it. The model is simple, but tests that catch all stuck-at faults also catch most real shorts and opens.

Some defects only make a path slower, so the logic computes the right answer, just too late. Transition or delay fault tests catch them: they launch a change and capture the result one fast clock later, at the chip's real speed. Other models cover shorts between neighbouring wires and faults inside cells. The share of modelled faults that the patterns detect is the test coverage, and production test usually aims for well above 95 percent stuck-at coverage, often above 99 percent.

Scan Chains

The difficulty with logic is reaching it. A flip-flop deep in a pipeline can only be set to a chosen value by running the right sequence of instructions, and its value can only be seen if it eventually reaches an output pin. Scan solves this. Every flip-flop gets a multiplexer at its input. In normal mode it takes its usual input; in test mode, the flip-flops are joined into long shift registers called scan chains.

A test then has three steps. Shift a chosen pattern into all the flip-flops, one bit per clock. Switch to normal mode for one clock, so that each flip-flop captures the output of the logic in front of it. Shift the captured values out and compare them with the expected values. Every flip-flop becomes both an input and an output of the test, so the logic between flip-flops can be tested as if it were simple combinational logic. Tools called ATPG, automatic test pattern generation, compute the patterns that detect the most faults.

Shifting is slow if the chains are long: a chip with a million flip-flops and one chain would need a million clocks per pattern. Designs use hundreds of chains in parallel, and test compression: a small decompressor on chip expands a few input bits into patterns for many chains, and a compactor squeezes the outputs back. This cuts test data and time by a large factor, often ten to a hundred.

Testing Memories

Memories are dense arrays of cells that scan can't reach, and they are often the largest part of an SoC's area. They are tested with memory built-in self-test, MBIST: a small controller next to each memory, or shared by a group, writes and reads patterns through the memory's ports and checks the results. The patterns, called march tests, step through every address in a set order, writing and reading 0s and 1s, so that they catch stuck cells, cells that disturb their neighbours, and faults in the address decoder.

Because large memories are so likely to contain a defect somewhere, they are built with spare rows and columns. When MBIST finds a failing cell, the chip's repair logic records which row or column to replace, usually in fuses blown at test, and from then on accesses to the bad row go to the spare. Repair turns many chips that would have failed into good ones, which matters greatly for yield.

JTAG and Test Access

The test equipment needs a way to control all this through a few pins. The standard way is JTAG, named after the group that defined it and standardized as IEEE 1149.1. It uses four or five pins: a clock, a data input, a data output, a mode select and an optional reset. Through them, the tester shifts instructions and data into a small state machine on the chip, the test access port controller, which selects what to do: run scan, start MBIST, read an identification code, or control the pins.

JTAG was first designed for boundary scan: a chain of cells at every I/O pin, which can drive and capture the pins. This lets a board maker check the connections between chips on a board without running any software. The same port is also used to reach on-chip debug, which is why it must be locked in production chips, as Security Architecture explains. Large SoCs connect many internal test features behind the port through a network of switchable chains, so that the tester can reach any block's test controller without passing through all the others.

Test at SoC Level

An SoC combines IP from many sources, as Buy, Reuse or Build: Choosing IP describes, and each block comes with its own test structures. Integrating them needs a plan. Blocks are often wrapped, so that each can be tested on its own with its inputs driven and outputs captured by the wrapper, and the tester can test several blocks in parallel. Hard blocks such as PLLs, analog circuits and high-speed interfaces have their own tests, often a loopback in which a transmitter's output is fed back to its own receiver.

The plan decides the test schedule: which blocks are tested together, how many pins and chains each needs, and the power limit. Test patterns switch far more flip-flops at once than normal operation does, so testing everything at the same time can draw more current than the package and the tester can supply, and drop the voltage enough to fail good chips. Schedules split tests into groups that stay within the limit.

DFT also affects the design itself. Scan multiplexers add a small delay and area to every flip-flop. Clocks must be controllable in test mode, so the clock generators need test multiplexers, and the clock domain crossings and resets described in Clock Architecture and Clock Domain Crossings must behave predictably during test. Logic that can't be controlled or observed, for example because a reset is generated internally, lowers coverage and needs test points added. That is why DFT is planned with the architecture, not added at the end.

Learning From Failures

Test does more than sort good chips from bad ones. When a chip fails, the failing patterns and the flip-flops that captured wrong values point to where the defect is. Diagnosis tools take these results and list the most likely faulty wires or cells. Across thousands of failing chips, the results show patterns: a certain cell, a certain layer, or a certain area of the wafer failing more often than others. The factory and the design team use this to find the cause, whether a process step that needs tuning or a layout feature that is too hard to make, and yield improves.

The same structures help with chips that fail later, returned from customers. A part that passed every test and failed in the field shows a gap in the test set, and the missing pattern or fault model is added for future production. This feedback is why test engineers watch the defect rates of shipped parts as closely as the yield on the tester.

The Cost of Test

A simple calculation shows why compression and parallel testing matter. Suppose a chip needs 10,000 patterns, each with chains of 500 flip-flops, shifted at 100 MHz. These values are assumptions for this example. Each pattern takes about 500 clocks, so all of them take 10,000 x 500 / 100 MHz = 50 ms. Without compression, with chains ten times longer, the same test would take 0.5 s. At a cost of a few cents per second of tester time, and millions of chips, the difference is large, and memory tests, analog tests and repeats at several voltages add to it.

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