Dynamic Voltage and Frequency Scaling

Dynamic voltage and frequency scaling, DVFS, changes a block's supply voltage and clock frequency while the chip runs, to match the work it has to do. Running slower at a lower voltage saves a great deal of energy, because power rises much faster than speed. Every phone, laptop and server uses it constantly. This article explains why voltage and frequency go together, how much energy scaling saves, when running fast and sleeping is better, how a frequency change is carried out safely, and how software decides the operating point.

11 min read | Intermediate

What You'll Learn

• Explain why frequency and voltage must change together
• Calculate power and energy at different operating points
• Compare slowing down with running fast and then sleeping
• Describe how hardware and software carry out a DVFS change

Why Voltage and Frequency Go Together

A gate's delay depends on its supply voltage: at a higher voltage, transistors switch faster, so the logic between flip-flops settles sooner, and the clock can run faster. At a lower voltage, the same logic is slower, so the clock must slow down too, or timing fails. Every frequency therefore has a minimum safe voltage. The pairs of voltage and frequency that a chip is characterized for are its operating performance points, often shortened to OPPs.

Now recall the relation for dynamic power from PPA Trade-offs and Amdahl's Law:

dynamic power = activity x capacitance x voltage^2 x frequency

Lowering the frequency alone cuts power in proportion, but the work takes longer by the same factor, so the energy for a task stays about the same. Lowering the voltage as well is where the saving comes from: energy per operation follows voltage squared. That is why DVFS changes both.

What It Saves

A model makes this concrete. A core has five operating points, from 0.65 V at 400 MHz to 1.05 V at 1.6 GHz. It runs a task of one billion cycles, with an assumed switched capacitance and a small leakage that scales with voltage. These values are assumptions for this example.

Running at the top point finishes the task four times sooner than the bottom one, but uses about 2.25 times the energy, and about 9 times the power. Every step up costs more energy per unit of work. If the task has a deadline that the slow point meets, running slowly saves more than half the energy. That is the whole idea of DVFS: run just fast enough.

The power figure matters too. At the top point, the core draws about 1.8 W, at the bottom about 0.2 W. Heat follows power, and a phone can't remove more than a few watts for long, so the top points can often be used only briefly. When the chip gets too hot, the system must drop to a lower point, which is called thermal throttling.

Race to Idle

There is a competing idea: run the task as fast as possible, then put the whole system to sleep. This is called race to idle. It wins when the rest of the system uses a lot of power while the core is active: memory, interconnect, display, regulators. That power is spent for as long as the task runs, so finishing sooner saves it.

Add an assumed 0.3 W of other system power to the model above, spent only while the task runs. At the bottom point, the energy becomes (0.20 + 0.3) x 2.5 s = about 1.25 J. At the top point, (1.82 + 0.3) x 0.625 s = about 1.32 J. At the middle point, 0.85 V and 1 GHz, (0.77 + 0.3) x 1.0 s = about 1.07 J, and at 0.75 V and 700 MHz, (0.43 + 0.3) x 1.43 s = about 1.05 J, the lowest of all five. Neither the slowest nor the fastest is best: once the rest of the system's power is counted, the minimum moves to a middle point. In practice, the right point depends on the whole platform, which is why operating systems learn it from measurements rather than assuming either rule.

Leakage pushes the same way. At very low voltages, gates are slow and the task takes long, so leakage, which is spent the whole time, becomes a larger share of the energy. Below a certain voltage, slowing down further costs more energy than it saves.

Changing the Operating Point

A change must be done in the right order, so that the logic never runs faster than its voltage allows:

going up:                             going down:
 1. raise the voltage                  1. lower the frequency
 2. wait until it is stable            2. lower the voltage
 3. raise the frequency

The voltage comes from a regulator, often in a separate power management chip, and changing it takes tens of microseconds or more. The frequency comes from a PLL or a divider. Changing a PLL's multiplier means it must relock, which takes time, so designs often switch the domain to another clock source during the change, through a glitch-free multiplexer, as Clock Architecture and Clock Domain Crossings explains, or step through dividers. A whole change typically takes tens of microseconds, so the operating point is changed every few milliseconds at most, not every few cycles.

Domains for DVFS

Each block that scales independently needs its own voltage and clock: a voltage domain. A phone chip might have separate domains for each CPU cluster, the GPU, and the rest of the chip. More domains allow finer control, but each needs a regulator, power routing, and level shifters on every signal crossing to a domain at a different voltage, as Power Domains and Power Management describes. Signals between domains running at unrelated frequencies also need clock domain crossings. So designers group blocks that tend to need the same speed into the same domain.

How Software Decides

An operating system component called a governor chooses the operating point. A simple governor watches how busy the core has been over the last few milliseconds, and raises the frequency when it is busy and lowers it when it is idle. More advanced ones use the scheduler's knowledge of each task's needs, and models of the chip's energy at each point, so that they can choose the most efficient point for the expected work. The goal is to finish work in time without running faster than needed.

The hardware helps by providing what the software needs: a table of operating points, registers to request a change, counters of cycles and busy time, and temperature sensors. Some systems move part of this into hardware or firmware, so that changes can happen faster than the operating system could manage.

Margins and Adaptive Voltage

The voltage for each operating point must work for the slowest chips that come off the production line, at the highest temperature, with a margin for noise on the supply. Most chips are faster than the slowest, so this wastes energy. Adaptive voltage scaling measures each chip's actual speed with on-chip monitors, such as ring oscillators or replicas of critical paths, and lowers the voltage to what that particular chip needs. Some chips are also binned at manufacture: each part is tested and given its own voltage table. Both can save a significant share of the power without changing the design.

Putting It Together on a Chip

From the chip designer's side, supporting DVFS means a list of concrete pieces. Each scalable domain needs its own regulator output or an on-chip regulator, a clock that can change, and level shifters and clock domain crossings at its edges. Timing must be closed at every operating point, not only the fastest: a path that is fine at 1.05 V may fail at 0.65 V if some cells slow down more than others at low voltage, so sign-off covers each corner of voltage and temperature that the table uses.

The memories need care too. SRAM cells often need a minimum voltage higher than the logic can run at, so a domain may keep its memories on a separate, steadier rail, or limit how low its lowest point goes. The register interface for requests, status and sensors must be documented for the software team, and the sequence for a change must be tested in simulation and on the first silicon, including a change that is interrupted by a reset or a temperature alarm.

Finally, the operating point table itself is a product decision made late, after silicon is measured. The hardware should allow it to be loaded from fuses or firmware rather than fixed in the design, so that each chip, or each product built on it, can use the points that its own measurements support. A small change late in the project then needs no new silicon at all.

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