SoC Design Interview Questions

SoC design interviews test whether you can reason about a whole system: how blocks share buses and memory, how clocks, resets and power are organized, and how a chip goes from requirements to tapeout. Interviewers start from a simple idea and push on it with "what happens when", "how would you size it" and "how would you check it". This article collects the questions that come up most often in interviews for SoC architecture, integration, design and verification roles, with worked answers, and shows how to approach a system question you haven't seen before.

13 min read | Intermediate

What You'll Learn

• Answer common questions on interconnects, memory and arbitration
• Work through bandwidth, latency and clock crossing calculations
• Explain clock, reset, power, security and safety architecture clearly
• Use a method for system questions you have not seen before

How to Answer

A good answer has a shape: state the idea in one sentence, give a small concrete example, then say what it costs or when it fails. For a sizing question, write down what you're assuming, such as a frequency, a bus width or a traffic rate, before you calculate, and check that the units come out right. If you don't know a detail, say what you do know and reason from it: interviewers care most about how you think.

For system questions, three habits help. Draw the blocks and the paths between them. Ask who shares what, since most system problems come from sharing. And ask how you would measure or verify your answer.

SoC Basics and Flow

What is an SoC, and why build one instead of several chips? A system on chip puts processors, memory, interconnect, peripherals and accelerators on one die. It cuts board area, power and cost, and makes on-chip communication far faster than between chips. The cost is a large, complex design that must be right before it is made. See What Is in an SoC.

What goes into a system architecture spec? The use cases and requirements, the block diagram, the address map, the clock, reset and power domains, the interconnect and its performance budgets, the boot flow, the security model and the interfaces. It is the single reference every team works from.

When would you buy IP instead of designing it? When the block is standard, such as a USB controller or DDR interface, when a vendor's version is proven in silicon, and when designing it would cost more time than it saves. Build it when it is a differentiator or no suitable IP exists.

Interconnect and Arbitration

Compare a shared bus, a crossbar and a network-on-chip. A shared bus lets one transfer through at a time: simple and small, but its throughput doesn't grow with more managers. A crossbar connects every manager to every target, allowing transfers to different targets at once, but its area grows with the product of the counts. A network-on-chip sends packets through routers, which scales to many blocks at the cost of latency. In one model with four managers and four targets, a crossbar carried 2.62 transfers per cycle under heavy load against 1.0 for a bus. See Buses, Crossbars and Networks-on-Chip.

Why do outstanding transactions matter? With one transaction at a time, bandwidth is the transaction size divided by the latency. Little's law says that to sustain bandwidth B with latency L, you need B x L bytes in flight. A 64-byte manager with 50 cycles of latency and one transaction outstanding gets about 1.2 bytes per cycle; with 16 outstanding, it reaches the full 16 bytes per cycle of the path. See Outstanding Transactions and Bursts.

What's wrong with fixed-priority arbitration? The lowest-priority manager can starve. In a model with three managers loading a target to 95 percent, the lowest-priority manager waited about 21 cycles on average, with 1 percent of its requests waiting over 100, while round robin kept every manager's average under 8 cycles. Weighted round robin gives a manager with deadlines, such as a display, more turns. See Arbitration and Quality of Service.

When does a DMA engine help? When data moves in blocks between memory and peripherals or between memories: the processor sets up the transfer and is free until an interrupt says it is done. For a few bytes, the setup costs more than copying by hand.

Memory System

Explain DRAM banks, rows and why access order matters. A DRAM is split into banks, each with rows. Reading needs the row opened into a row buffer first; accesses to the open row are fast, and a different row needs the current one closed and the new one opened. Sequential accesses mostly hit the open row; random ones keep switching rows. See DRAM Organization.

What does a memory controller's scheduler do? It reorders requests to hit open rows and keep banks busy. First-ready, first-come-first-served scheduling serves row hits first. In a model with two streams sharing banks, FR-FCFS raised data bus utilization from about 13 percent to 76 percent over plain in-order service. See Memory Controllers and Scheduling.

How would you check whether a memory system has enough bandwidth? List every manager's bandwidth in the worst use case, add them, and compare with what the DRAM can deliver at a realistic efficiency, not its peak. Leave margin, and check the deadline-driven managers separately with latency, since average bandwidth doesn't show bursts.

Scratchpad or cache? A scratchpad is SRAM at a fixed address that software manages: predictable, no tag cost, but software must move data. A cache works automatically but its timing depends on the data. Real-time and accelerator code often prefers scratchpads.

Interrupts, Timers and Multicore

What does an interrupt controller do? It collects interrupt lines from all devices, holds pending state, applies priorities and enables, and signals the right core. The core claims the highest-priority pending interrupt, handles it, and tells the controller it is complete.

Level or edge-triggered interrupts? A level interrupt stays asserted until software clears the cause, so it can't be lost but must be cleared at the source. An edge interrupt is a pulse that is latched; it can be lost or merged if two arrive before software reads it.

What is a watchdog and how should it be designed? A timer that resets the chip unless software restarts it in time. It should be hard to disable by accident, run from a clock software can't stop, and its reset should record that it fired. See Timers and Watchdogs.

Why does a multicore SoC need cache coherence, and what does it cost? Each core's cache can hold a copy of the same line; without coherence, one core could read stale data. Snooping or directories keep copies consistent, at the cost of traffic, latency and logic.

Clocks, Resets and Power

Why do signals crossing clock domains need synchronizers? A flip-flop sampling a signal that changes near its clock edge can go metastable. Two flip-flops in series give it a cycle to settle. With one set of assumed parameters, one flip-flop gave a mean time between failures of about 12 days; two gave over 10²⁰ years. Multi-bit values need a handshake or an asynchronous FIFO with Gray-coded pointers. See Clock Architecture and Clock Domain Crossings.

What is reset synchronization? Assert asynchronously, so the reset works even without a clock, and deassert synchronously, through a synchronizer, so that all flip-flops leave reset on the same edge. See Reset Architecture and Reset Domain Crossings.

What do isolation cells and retention registers do? When a domain is powered off, its outputs float; isolation cells clamp them to safe values for the domains that stay on. Retention registers keep chosen state in a small always-on latch so the domain can resume without starting over. See Power Domains and Power Management.

Why does DVFS save energy? Dynamic power is C V² f. Lowering frequency alone stretches the task with little energy saving; lowering voltage cuts energy per operation by V². Raise voltage before frequency, and lower frequency before voltage.

Security, Safety and Test

What is a root of trust? The first trusted component, usually ROM code and keys fixed in the chip, that checks each boot stage's signature before running it. See Security Architecture.

How would you stop a DMA engine from reading secure memory? Tag every access with its security state, check the tags with a firewall at the target, and make sure the DMA engine's accesses carry the tag of the software that programmed it.

What is lockstep, and what does it cost? Two identical cores run the same code, one slightly delayed, and a comparator checks their outputs. It detects faults within cycles, at about twice the area and power of one core. See Safety and Reliability.

How is a chip tested in manufacturing? Scan chains turn flip-flops into shift registers so ATPG patterns can test the logic; MBIST tests memories; JTAG gives the tester access. See Design for Test at SoC Level.

Methodology

How would you verify an SoC, as opposed to its blocks? Focus on connections, the address map, interactions and system features: C tests on the processor, connectivity and register checks, scenario tests, then emulation for operating system boot. See SoC-Level Verification Strategy.

Why use emulation or FPGA prototypes? Simulation of a full SoC runs at hundreds to thousands of cycles per second, too slow to boot an operating system. Emulation runs at about a megahertz with good visibility; FPGA prototypes at tens of megahertz for software teams.

What must be true before tapeout? Verification and coverage goals met, timing met at all corners, DRC and LVS clean, equivalence proven, power intent verified, test inserted, boot ROM frozen, and every waiver reviewed. See Tapeout Readiness and SoC Sign-Off.

Approaching an Unknown Question

For a system design question, work in a fixed order: clarify the use cases and the numbers, such as resolution, frame rate and battery life; list the blocks; draw the data paths and estimate the bandwidth on each; choose the interconnect and memory; then add clocks, power domains, security and test. Say your assumptions out loud and check them against the numbers as you go.

For a debugging question, such as "the display flickers when the camera runs", start from what is shared. Both use memory bandwidth; is the display's latency budget met under load? Is its buffer large enough? Is its priority high enough? Propose a measurement that would tell each cause apart. That shows a method, which is what the question is testing.

Common Mistakes