SystemVerilog Static Cast

Static cast is a SystemVerilog feature that allows converting an expression from one data type to another at compile time.

Syntax

'(value or variable or expression)

Here are some of the properties of static cast in SystemVerilog:


  module tb;
  
  	initial begin      
      $display("data=%0d", int'("Hello World"));
 	end
  endmodule

Simulation Log

	xcelium> run
	data=1869769828
	xmsim: *W,RNQUIE: Simulation is complete.

Static cast enforces type safety, meaning that it will not allow casting between incompatible data types.
Evaluated at compile time, so it does not affect the simulation performance
Applicable to variables and expressions


    module tb;
  
  	initial begin
      $display("data=%0.3f", int'(3.4 + 2 * 1.5));
 	end
  endmodule

Simulation Log

  	xcelium> run
	data=6.000
	xmsim: *W,RNQUIE: Simulation is complete.

When casting from a larger data type to a smaller one, static cast truncates the least significant bits of the source value.


  module tb;
  	int 	data;
  
  	initial begin
  		data = int'(3.145);
  		$display("data=%0.3f", data);
 	end
  endmodule

Simulation Log

  	xcelium> run
	data=3.000
	xmsim: *W,RNQUIE: Simulation is complete.