SystemVerilog randcase

SystemVerilog's randcase statement is a case-like construct that randomly picks exactly one of its branches to execute, weighted by positive integer values you assign to each branch. Unlike an ordinary case statement, where the branch that runs depends on comparing an expression against each item, no expression decides which randcase branch runs — the solver does, based purely on the weights you give it.

6 min read | Intermediate Level

What You'll Learn

• What randcase is and how it differs from an ordinary case statement
• How branch weights convert into selection probabilities
• What happens with a zero-weight branch, and with every branch weighted zero
• How SystemVerilog picks a branch internally from a single random draw

Syntax: randcase

Each branch is a positive integer weight followed by a colon and a statement to execute if that branch is chosen:

randcase
	item 	: 	statement;
	...
endcase

Parameters:

• item — a non-negative integer expression representing that branch's weight (zero is legal, and simply means the branch is never taken)
• statement — the statement executed if this branch is selected

The probability of any one branch being selected is that branch's weight divided by the sum of all the weights in the block.

Weighted Random Branch Selection

In the example below, the weights are 1, 5, and 3, which sum to 9. That makes the first branch's probability 1/9 (11.11%), the second branch's probability 5/9 (55.56%), and the third branch's probability 3/9 (33.33%):

module tb;
	initial begin
      for (int i = 0; i < 10; i++)
      	randcase
        	1 	: 	$display ("Wt 1");
      		5 	: 	$display ("Wt 5");
      		3 	: 	$display ("Wt 3");
      	endcase
    end
endmodule

Output

ncsim> run
Wt 5
Wt 5
Wt 3
Wt 5
Wt 1
Wt 3
Wt 5
Wt 3
Wt 3
Wt 5
ncsim: *W,RNQUIE: Simulation is complete.

Note that Wt 5 appeared the most (the highest-probability branch), Wt 1 appeared the least (the lowest-probability branch), and Wt 3 landed somewhere in between — exactly what the weights predict over enough iterations.

Zero-Weight Branches Are Skipped

If a branch specifies a weight of zero, that branch is simply never taken:

module tb;
	initial begin
      for (int i = 0; i < 10; i++)
      	randcase
        	0 	: 	$display ("Wt 0");
      		5 	: 	$display ("Wt 5");
      		3 	: 	$display ("Wt 3");
      	endcase
    end
endmodule

Output

ncsim> run
Wt 5
Wt 5
Wt 3
Wt 5
Wt 5
Wt 3
Wt 5
Wt 3
Wt 3
Wt 5
ncsim: *W,RNQUIE: Simulation is complete.

Wt 0 never appears in the output — with a weight of 0, that branch contributes nothing to the probability calculation, so it can never be the one selected.

What Happens When All Weights Are Zero

Weighting every branch at zero doesn't make sense in practice, but SystemVerilog defines what happens if it occurs: no branch is taken, and the simulator issues a run-time warning instead of a compile-time error.

module tb;
	initial begin
      for (int i = 0; i < 10; i++)
      	randcase
        	0 	: 	$display ("Wt 0.1");
      		0 	: 	$display ("Wt 0.2");
      		0 	: 	$display ("Wt 0.3");
      	endcase
    end
endmodule

Output

ncsim> run
ncsim: *W,RANDNOB: The sum of the weight expressions in the randcase statement is 0.
No randcase branch was taken.
            File: ./testbench.sv, line = 4, pos = 14
           Scope: tb.unmblk1
            Time: 0 FS + 0

ncsim: *W,RANDNOB: The sum of the weight expressions in the randcase statement is 0.
No randcase branch was taken.
            File: ./testbench.sv, line = 4, pos = 14
           Scope: tb.unmblk1
            Time: 0 FS + 0

ncsim: *W,RANDNOB: The sum of the weight expressions in the randcase statement is 0.
No randcase branch was taken.
            File: ./testbench.sv, line = 4, pos = 14
           Scope: tb.unmblk1
            Time: 0 FS + 0
  
            ...

module tb;
	initial begin
      repeat (10) begin
      	randcase
        	10 	: 	$display ("READ");
      		10 	: 	$display ("WRITE");
      		1 	: 	$display ("ERROR");
      	endcase
      end
    end
endmodule