SystemVerilog offers much flexibility in building complicated data structures through the different types of arrays.
Static Arrays
A static array is one whose size is known before compilation time. In the example shown below, a static array of 8-bit wide is declared, assigned some value and iterated over to print its value.
module tb;
bit [7:0] m_data; // A vector or 1D packed array
initial begin
// 1. Assign a value to the vector
m_data = 8'hA2;
// 2. Iterate through each bit of the vector and print value
for (int i = 0; i < $size(m_data); i++) begin
$display ("m_data[%0d] = %b", i, m_data[i]);
end
end
endmodule
Static arrays are further categorized into packed and unpacked arrays.
bit [2:0][7:0] m_data; // Packed
bit [15:0] m_mem [10:0]; // Unpacked
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Unpacked arrays may be fixed-size arrays, dynamic arrays, associative arrays or queues.
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Dynamic Arrays
A dynamic array is one whose size is not known during compilation, but instead is defined and expanded as needed during runtime. A dynamic array is easily recognized by its empty square brackets [ ]
.
int m_mem []; // Dynamic array, size unknown but it holds integer values
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Associative Arrays
An associative array is one where the content is stored with a certain key. This is easily recognized by the presence of a data type inside its square brackets [ ]
. The key is represented inside the square brackets.
int m_data [int]; // Key is of type int, and data is also of type int
int m_name [string]; // Key is of type string, and data is of type int
m_name ["Rachel"] = 30;
m_name ["Orange"] = 2;
m_data [32'h123] = 3333;
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Queues
A queue is a data type where data can be either pushed into the queue or popped from the array. It is easily recognized by the $
symbol inside square brackets [ ]
.
int m_queue [$]; // Unbound queue, no size
m_queue.push_back(23); // Push into the queue
int data = m_queue.pop_front(); // Pop from the queue
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