SystemVerilog Arrays

SystemVerilog offers a lot of flexibility for building data structures through its different array types. Picking the right one matters: a testbench scoreboard, a sparse lookup table, and a fixed-width register file all call for a different kind of array, and each one is recognized by a distinct declaration syntax.

This article gives a quick overview of the four array categories — static, dynamic, associative, and queue — so you can recognize each one and know where to dig deeper.

6 min read | Intermediate Level

What You'll Learn

• The four array categories in SystemVerilog and how to recognize each one
• How static arrays split further into packed and unpacked forms
• When to reach for a dynamic array, an associative array, or a queue
• Where to go for a deeper dive into each array type

Static Arrays

A static array is one whose size is known before compilation. The example below declares an 8-bit wide static array, assigns it a value, and iterates over it to print each bit.

module tb;
	bit [7:0] 	m_data; 	// A vector or 1D packed array

	initial begin
		// 1. Assign a value to the vector
		m_data = 8'hA2;

		// 2. Iterate through each bit of the vector and print value
		for (int i = 0; i < $size(m_data); i++) begin
			$display ("m_data[%0d] = %b", i, m_data[i]);
		end
	end
endmodule

Output

ncsim> run
m_data[0] = 0
m_data[1] = 1
m_data[2] = 0
m_data[3] = 0
m_data[4] = 0
m_data[5] = 1
m_data[6] = 0
m_data[7] = 1
ncsim: *W,RNQUIE: Simulation is complete.

Static arrays are further categorized into packed and unpacked arrays, based on whether the dimensions are declared before or after the variable name.

bit [2:0][7:0] 	m_data; 			    // Packed
bit [15:0] 		  m_mem [10:0]; 		// Packed + Unpacked

Learn more about SystemVerilog Packed Arrays

Unpacked arrays may be fixed-size arrays, dynamic arrays, associative arrays, or queues — the rest of this article covers those non-fixed-size forms.

Learn more about SystemVerilog Unpacked Arrays

Static arrays (packed or unpacked-fixed-size) are the default choice for RTL and for any testbench structure whose size you already know, like a fixed-depth register file or a bus with a known number of lanes.

Dynamic Arrays

A dynamic array is one whose size isn't known at compile time — it's allocated and resized during runtime instead. It's easily recognized by its empty square brackets [ ].

int 		m_mem []; 	// Dynamic array, size unknown but it holds integer values

Learn more about SystemVerilog Dynamic Arrays

Dynamic arrays are a good fit when you know you're storing a list of same-typed elements, but the count depends on something learned at runtime — for example, the number of packets to send for a given test scenario.

Associative Arrays

An associative array stores content against a key rather than a sequential index. It's recognized by a data type sitting inside the square brackets — that type is the key.

int 		m_data [int]; 			// Key is of type int, and data is also of type int
int 		m_name [string]; 		// Key is of type string, and data is of type int

m_name ["Rachel"] = 30;
m_name ["Orange"] = 2;

m_data [32'h123] = 3333;

Learn more about SystemVerilog Associative Arrays

Associative arrays are the natural fit for sparse data, like tracking scoreboard entries by transaction ID or counting coverage hits by an address that could be anywhere in a huge memory space, without allocating storage for every possible index.

Queues

A queue lets you push data in and pop data out from either end. It's recognized by the $ symbol inside the square brackets.

int 	m_queue [$]; 		// Unbound queue, no size


m_queue.push_back(23); 		// Push into the queue

int data = m_queue.pop_front(); // Pop from the queue

Learn more about SystemVerilog Queues

Queues are the go-to structure for scoreboards, transaction pipelines, and any place you need strict ordering with fast insertion and removal at either end — something a plain dynamic array doesn't give you as conveniently.

Common Mistakes

// Associative array: key = transaction ID, data = the outstanding request
my_transaction pending_reqs [bit [31:0]];

// Add an outstanding request
pending_reqs[tx_id] = req;

// Look up and remove it once the response arrives
if (pending_reqs.exists(resp_id)) begin
  my_transaction original_req = pending_reqs[resp_id];
  pending_reqs.delete(resp_id);
end