SystemVerilog solve before

The SystemVerilog constraint solver, by default, tries to give a uniform distribution across the entire space of valid combinations — not necessarily a uniform distribution for each individual variable on its own. solve...before can change that, shifting probability so certain corner cases get chosen far more often than they otherwise would. This article compares an example with and without it.

14 min read | Intermediate Level

What You'll Learn

• Why the solver aims for a uniform distribution across the whole solution space by default, not independently for each variable
• How that default behavior can make one variable's value far less likely than you might expect, just because it happens to leave fewer combinations available
• solve...before, and how it gives a variable an independent, even distribution instead
• The restrictions on which variables can be ordered this way

Random Distribution Example

A 3-bit random variable b has 8 legal values, and the probability of b landing on any one of them is the same:

class ABC;
	rand bit [2:0]  b;
endclass

module tb;
	initial begin
		ABC abc = new;
		for (int i = 0; i < 10; i++) begin
			abc.randomize();
			$display ("b=%0d", abc.b);
		end
	end
endmodule

Output

ncsim> run
b=7
b=7
b=2
b=1
b=6
b=4
b=2
b=4
b=0
b=1
ncsim: *W,RNQUIE: Simulation is complete.

Repeated values in the output don't mean anything special — a previous randomization has no effect on the current one, so the randomizer is free to pick any of the 8 values regardless of what came before. Every one of the 8 legal values has an equal chance of being chosen.

Without solve...before

Now consider two random variables, where the constraint ensures b gets 0x3 whenever a is 1:

class ABC;
  rand  bit			a;
  rand  bit [1:0] 	b;
  
  constraint c_ab { a -> b == 3'h3; }
endclass

module tb;
  initial begin
    ABC abc = new;
    for (int i = 0; i < 8; i++) begin
      abc.randomize();
      $display ("a=%0d b=%0d", abc.a, abc.b);
    end
  end
endmodule

Output

ncsim> run
a=0 b=0
a=0 b=1
a=0 b=0
a=0 b=1
a=0 b=2
a=1 b=3
a=0 b=3
a=0 b=3
ncsim: *W,RNQUIE: Simulation is complete.

a and b are determined together, not one after the other. When a is 0, b can take any of 4 values — 4 valid combinations. When a is 1, b can only be 3 — just 1 valid combination. That's 5 valid (a, b) pairs total, and by default the solver treats all 5 as equally likely:

Because only 1 of those 5 equally-likely combinations has a=1, the overall probability of a ending up 1 is just 1/5, or 20% — noticeably less than the 50/50 you might expect from a single-bit variable on its own.

With solve...before

SystemVerilog lets you order variables so one is chosen independently of another, using the solve keyword:

class ABC;
  rand  bit			a;
  rand  bit [1:0] 	b;
  
  constraint c_ab { a -> b == 3'h3;

  				  // Tells the solver that "a" has
  				  // to be solved before attempting "b"
  				  // Hence value of "a" determines value
  				  // of "b" here
                  	solve a before b;
                  }
endclass

module tb;
  initial begin
    ABC abc = new;
    for (int i = 0; i < 8; i++) begin
      abc.randomize();
      $display ("a=%0d b=%0d", abc.a, abc.b);
    end
  end
endmodule

Output

ncsim> run
a=1 b=3
a=1 b=3
a=0 b=1
a=0 b=0
a=0 b=0
a=0 b=1
a=1 b=3
a=0 b=2
ncsim: *W,RNQUIE: Simulation is complete.

Compare this against the previous output — a=1 now shows up far more often. a is solved first, and whatever it gets determines how b is solved next:

Because a is now solved on its own, the probability of it landing on either 0 or 1 is a flat 50%. Only once a is settled does the solver work out b — freely among 4 values if a=0 (each getting a quarter of that 50%, or 12.5% overall), or forced straight to 3 if a=1 (keeping the whole 50%, since there's nothing left to choose). P(a=1) has jumped from 20% to 50%, exactly the shift solve...before is meant to produce.

Restrictions

A few restrictions apply to solve...before:

• randc variables aren't allowed, since they're always solved first regardless
• Variables should be integral values
• There must be no circular dependency in the ordering, such as solve a before b combined with solve b before a

Common Beginner Mistakes