Assertions $past, $sampled, $changed

SystemVerilog $rose, $fell, $stable covered detecting an edge or the absence of one. This article covers three more sampled-value system functions: $past, for reaching back further than just "the previous cycle"; $sampled, for reading a signal's assertion-visible value from procedural code; and $changed, the direct logical complement of $stable.

11 min read | Intermediate Level

What You'll Learn

• How $past retrieves a signal's value from a specific number of cycles ago, not just the immediately previous one
• How $past's optional gating argument skips cycles where a condition wasn't true
• What $sampled is for, and why it matters specifically inside procedural code
• Why $changed is just the logical opposite of $stable

$past: Reaching Back Further Than One Cycle

$past(expr) returns the value expr had one clock tick ago — the classic use case is checking a registered signal against the value that fed it:

// Checks that out correctly holds whatever in was one cycle earlier -
// a straightforward 1-cycle pipeline register check
assert property (@(posedge clk) out == $past(in));

Given in sampled as 5, 7, 2, 9 across four consecutive cycles, a correctly-implemented 1-cycle delay register (out <= in; every cycle) produces out values of 5, 7, 2 starting from the second cycle onward — and checking out == $past(in) passes at every one of those cycles, since each out value exactly matches what in was one cycle before it.

Now suppose the design has a bug — an off-by-one delay, lagging by 2 cycles instead of 1. At the cycle where out should show in's value from one cycle back (7), it instead still shows the value from two cycles back (5). The assertion catches this immediately: $past(in) correctly evaluates to 7, but out is 5 — a clear failure, exactly identifying the pipeline timing bug.

Looking Back More Than One Cycle

A second argument specifies how many cycles back to look:

assert property (@(posedge clk) out2 == $past(in, 2));   // 2-cycle pipeline stage

Skipping Cycles With a Gating Argument

A third, optional argument gates which cycles actually count as "history" — instead of strictly N ticks ago in absolute time, $past looks back to the most recent cycle where the gating condition was true, skipping over any cycles where it wasn't:

// Compares captured against data's value from the most recent cycle
// where enable was actually high - not just literally 1 cycle ago
assert property (@(posedge clk) captured == $past(data, 1, enable));

This is useful whenever a value is only meant to update on specific qualifying cycles — without the gating argument, $past would compare against whatever data happened to be exactly one cycle back, even on a cycle where enable was low and nothing was actually supposed to be captured.

$sampled: Reading a Signal's Assertion-Visible Value

$sampled(expr) returns the same preponed-region value an assertion would use, but callable from ordinary procedural code — useful when you want a $display or other procedural statement to show exactly the value an assertion actually evaluated, rather than whatever the signal's live value happens to be at the exact point that procedural code executes:

if (some_condition)
  $display ("Value seen by the assertion: %0d", $sampled(data));

Without $sampled, procedural code reading data directly could, in principle, see a value that's already moved on from what the assertion itself sampled in the preponed region — $sampled guarantees the two match.

$changed: The Opposite of $stable

$changed(expr) is true exactly when expr's value differs from its previous sampled value — the direct logical complement of $stable. Reusing the same signal trace verified in the $rose/$fell/$stable article:

At every one of these samples, $changed(a) is exactly the opposite of $stable(a) — wherever the value held steady, $stable passes and $changed fails, and wherever it moved, the reverse.

Even at 10ns — the very first sample, with no earlier posedge yet — $stable and $changed still land on exactly opposite results. Before any real prior tick exists, both functions compare against a's default sampled value (0 for a 2-state bit) instead of being left undefined, so the same complementary relationship holds there too.

Common Beginner Mistakes

assert property (@(posedge clk) stage3_out == $past(data_in, 3));