SystemVerilog $rose, $fell, $stable

A sequence is a simple building block in SystemVerilog assertions that can represent certain expressions to aid in creating more complex properties. Even a single signal name, on its own, is already a complete (if very simple) sequence.

11 min read | Intermediate Level

What You'll Learn

• How a single signal name can itself be a complete sequence
• How $rose and $fell detect edges specifically, comparing against a default value when there's no earlier real sample yet
• How $stable differs from both, checking for the absence of any transition at all
• Why all three functions, applied to the exact same signal trace, classify each cycle differently

A Simple Sequence

module tb;
  	bit a;
  	bit clk;
  
	// This sequence states that a should be high on every posedge clk
  	sequence s_a;
      @(posedge clk) a;
    endsequence
  
  	// When the above sequence is asserted, the assertion fails if 'a'
  	// is found to be not high on any posedge clk
  	assert property(s_a);

  
	always #10 clk = ~clk;
  
	initial begin
      for (int i = 0; i < 10; i++) begin  
        a = $random;
        @(posedge clk);
  
        // Assertion is evaluated in the preponed region and
        // use $display to see the value of 'a' in that region
        $display("[%0t] a=%0d", $time, a);
      end
      #20 $finish;
    end
endmodule

Output

Compiler version P-2019.06-1; Runtime version P-2019.06-1;  Jan 14 06:32 2020
[10] a=0
"testbench.sv", 12: tb.unnamed$$_0: started at 10ns failed at 10ns
	Offending 'a'
[30] a=1
[50] a=1
[70] a=1
[90] a=1
[110] a=1
[130] a=1
[150] a=0
"testbench.sv", 12: tb.unnamed$$_0: started at 150ns failed at 150ns
	Offending 'a'
[170] a=1
[190] a=1
$finish called from file "testbench.sv", line 27.
$finish at simulation time                  210

This same a trace — 0, 1, 1, 1, 1, 1, 1, 0, 1, 1 across the ten sampled edges — is reused in every example below, so you can directly compare how each system function classifies the exact same signal differently.

$rose

The system function $rose detects a positive edge of the given signal. Because SystemVerilog assertions evaluate in the preponed region, $rose compares the signal's value across two samples — when the value is 0 on one and 1 on the next, a positive edge is assumed to have happened. Before the very first real sample, the "previous" value used for that comparison is the signal's default (0 for a 2-state bit), so a rise can in principle register immediately; in this particular trace, though, it genuinely takes until the second clock to see one:

module tb;
  	bit a;
  	bit clk;
  
	// This sequence states that 'a' should rise on every posedge clk
  	sequence s_a;
      @(posedge clk) $rose(a);
    endsequence
  
  	// When the above sequence is asserted, the assertion fails if
  	// posedge 'a' is not found on every posedge clk
  	assert property(s_a);

  
	// Rest of the testbench stimulus
endmodule

A positive edge is detected and the assertion passes at 30ns — a is 0 at 10ns and 1 at 30ns, so the rise completes right there. The same happens again at 170ns.

Compiler version P-2019.06-1; Runtime version P-2019.06-1;  Jan 14 06:58 2020
[10] a=0
"testbench.sv", 12: tb.unnamed$$_0: started at 10ns failed at 10ns
	Offending '$rose(a)'
[30] a=1
[50] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 50ns failed at 50ns
	Offending '$rose(a)'
[70] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 70ns failed at 70ns
	Offending '$rose(a)'
[90] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 90ns failed at 90ns
	Offending '$rose(a)'
[110] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 110ns failed at 110ns
	Offending '$rose(a)'
[130] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 130ns failed at 130ns
	Offending '$rose(a)'
[150] a=0
"testbench.sv", 12: tb.unnamed$$_0: started at 150ns failed at 150ns
	Offending '$rose(a)'
[170] a=1
[190] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 190ns failed at 190ns
	Offending '$rose(a)'
$finish called from file "testbench.sv", line 27.
$finish at simulation time                  210

$fell

$fell works the same way as $rose, but detects the opposite transition — when the value is 1 on one edge and 0 on the next, a negative edge is assumed to have happened:

module tb;
  	bit a;
  	bit clk;
  
	// This sequence states that 'a' should fall on every posedge clk
  	sequence s_a;
      @(posedge clk) $fell(a);
    endsequence
  
  	// When the above sequence is asserted, the assertion fails if
  	// negedge 'a' is not found on every posedge clk
  	assert property(s_a);

  
	// Rest of the testbench stimulus
endmodule

Notice 30ns and 170ns both show a marked transition (0->1), yet both still FAIL — a transition genuinely happened, just the wrong kind of transition for what $fell is checking. A negative edge is only actually detected, and the assertion passes, at 150ns.

Compiler version P-2019.06-1; Runtime version P-2019.06-1;  Jan 14 07:09 2020
[10] a=0
"testbench.sv", 12: tb.unnamed$$_0: started at 10ns failed at 10ns
	Offending '$fell(a)'
[30] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 30ns failed at 30ns
	Offending '$fell(a)'
[50] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 50ns failed at 50ns
	Offending '$fell(a)'
[70] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 70ns failed at 70ns
	Offending '$fell(a)'
[90] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 90ns failed at 90ns
	Offending '$fell(a)'
[110] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 110ns failed at 110ns
	Offending '$fell(a)'
[130] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 130ns failed at 130ns
	Offending '$fell(a)'
[150] a=0
[170] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 170ns failed at 170ns
	Offending '$fell(a)'
[190] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 190ns failed at 190ns
	Offending '$fell(a)'
$finish called from file "testbench.sv", line 27.
$finish at simulation time                  210

$stable

$stable checks something different from either edge-detection function: that the value hasn't changed at all between the current and previous sample, regardless of which direction a change would have gone:

module tb;
  	bit a;
  	bit clk;
  
	// This sequence states that 'a' should be stable on every clock
	// and should not have posedge/negedge at any posedge clk
  	sequence s_a;
      @(posedge clk) $stable(a);
    endsequence
  
  	// When the above sequence is asserted, the assertion fails if
  	// 'a' toggles at any posedge clk
  	assert property(s_a);

  
	// Rest of the testbench stimulus
endmodule

Compiler version P-2019.06-1; Runtime version P-2019.06-1;  Jan 14 07:12 2020
[10] a=0
[30] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 30ns failed at 30ns
	Offending '$stable(a)'
[50] a=1
[70] a=1
[90] a=1
[110] a=1
[130] a=1
[150] a=0
"testbench.sv", 12: tb.unnamed$$_0: started at 150ns failed at 150ns
	Offending '$stable(a)'
[170] a=1
"testbench.sv", 12: tb.unnamed$$_0: started at 170ns failed at 170ns
	Offending '$stable(a)'
[190] a=1
$finish called from file "testbench.sv", line 27.
$finish at simulation time                  210

Comparing All Four on the Same Trace

Since every example in this article uses the exact same a trace, here's all four side by side:

Common Beginner Mistakes