SystemVerilog Abstract Class

SystemVerilog prohibits a class declared as virtual from being directly instantiated — this is called an abstract class. However, an abstract class can still be extended to form other sub-classes, which can then be instantiated normally. This is useful for enforcing that testcase developers always extend a base class to form another class for their needs — so base classes are commonly declared virtual, though it isn't mandatory.

11 min read | Intermediate Level

What You'll Learn

• What makes a class "abstract" in SystemVerilog, and why it can't be instantiated directly
• How an abstract class can still be extended into usable subclasses
• What a pure virtual method is, and why its implementation is mandatory in every subclass
• Why abstract base classes are a common pattern for enforcing a required interface

Syntax

virtual class 
	// class definition
endclass

A Normal Class

For comparison, here's an ordinary class, instantiated normally:

class BaseClass;
	int data;

	function new();
		data = 32'hc0de_c0de;
	endfunction
endclass

module tb;
	BaseClass base;
	initial begin
		base = new();
		$display ("data=0x%0h", base.data);
	end
endmodule

Output

ncsim> run
data=0xc0dec0de
ncsim: *W,RNQUIE: Simulation is complete.

Making It Abstract With virtual

Declaring the exact same class virtual turns it into an abstract class:

virtual class BaseClass;
	int data;

	function new();
		data = 32'hc0de_c0de;
	endfunction
endclass

module tb;
	BaseClass base;
	initial begin
		base = new();
		$display ("data=0x%0h", base.data);
	end
endmodule

Output

		base = new();
		   |
ncvlog: *E,CNIABC (testbench.sv,12|5): An abstract (virtual) class cannot be instantiated.

The exact same code that worked a moment ago now fails to compile, purely because of the added virtual keyword on the class declaration.

Extending an Abstract Class

Abstract classes can be extended just like any other SystemVerilog class, using extends:

virtual class BaseClass;
	int data;

	function new();
		data = 32'hc0de_c0de;
	endfunction
endclass

class ChildClass extends BaseClass;
	function new();
		data = 32'hfade_fade;
	endfunction
endclass

module tb;
	ChildClass child;
	initial begin
		child = new();
		$display ("data=0x%0h", child.data);
	end
endmodule

Output

ncsim> run
data=0xfadefade
ncsim: *W,RNQUIE: Simulation is complete.

ChildClass's constructor never writes super.new() explicitly, but since BaseClass's constructor takes no required arguments, SystemVerilog still calls it implicitly first — briefly setting data to 0xc0dec0de — before ChildClass's own constructor body runs and immediately overwrites it to 0xfadefade. See SystemVerilog Class Constructor for more on this implicit-call behavior.

Pure Virtual Methods

A virtual method inside an abstract class can be declared with the keyword pure, making it a pure virtual method. Such a method only specifies a prototype within the abstract class — no body at all — and its actual implementation is left entirely to the subclasses that extend it.

Pure Method Example

virtual class BaseClass;
	int data;

	pure virtual function int getData();
endclass

class ChildClass extends BaseClass;
	virtual function int getData();
		data = 32'hcafe_cafe;
		return data;
	endfunction
endclass

module tb;
	ChildClass child;
	initial begin
		child = new();
		$display ("data = 0x%0h", child.getData());
	end
endmodule

The pure virtual method's prototype and its implementation must share the same arguments and return type.

Output

ncsim> run
data = 0xcafecafe
ncsim: *W,RNQUIE: Simulation is complete.

Notice BaseClass's getData() declaration ends right at the semicolon — no endfunction, no body at all. All of the actual logic lives entirely inside ChildClass's own implementation.

Common Beginner Mistakes

virtual class BaseClass;
  int data;

  pure virtual function int getData();
  pure virtual function int getDoubled();
endclass

class ChildClass extends BaseClass;
  virtual function int getData();
    data = 32'hcafe_cafe;
    return data;
  endfunction

  virtual function int getDoubled();
    return data * 2;
  endfunction
endclass

module tb;
  ChildClass child;
  initial begin
    child = new();
    $display ("data = 0x%0h", child.getData());
    $display ("doubled = 0x%0h", child.getDoubled());
  end
endmodule