SystemVerilog Interface Bundles

A module that accepts an interface as a port can reference that interface in one of two ways: by naming the exact interface type it expects, or by using a generic placeholder that accepts any interface passed to it. Which one you reach for depends on whether the module needs to work with one specific interface definition, or stay flexible as that definition evolves.

6 min read | Intermediate Level

What You'll Learn

• The difference between a named interface bundle and a generic interface bundle in a module's port list
• Why a generic interface bundle is useful when interface definitions change over time
• The ANSI-style port declaration restriction that applies to generic interface ports
• How partial implicit port connections (.*) work alongside a generic interface port

Named vs Generic Interface Bundles

There are two ways a design can accept an interface:

• By using an existing interface name, to specifically require only that one interface
• By using a generic interface handle, to which any interface can be passed

The generic method works best when interface definitions get updated to newer versions under a different name, while older designs still need to keep working against whatever interface they were built for.

Example Using a Named Bundle

Here, the design references the actual interface name to access its signals. Both myDesign and yourDesign declare a port in their port list called if0, of type myInterface:

module myDesign  (  myInterface  if0,
                    input logic  clk);
	always @ (posedge clk)
		if (a.ack)
			if0.gnt <= 1;

	...
endmodule

module yourDesign (  myInterface 	if0,
					 input logic 	clk);
	...

endmodule

module tb;
	logic clk = 0;

	myInterface 	_if;

	myDesign 	md0 	(_if, clk);
	yourDesign	yd0 	(_if, clk);

endmodule

module myDesign  ( interface  a,
                   input logic  clk);
  
	always @ (posedge clk)
		if (if0.ack)
			if0.gnt <= 1;

	...
endmodule

module yourDesign (  interface 		b,
					 input logic 	clk);
	...

endmodule

module tb;
	logic clk = 0;

	myInterface  _if;

	myDesign 	md0 ( .*, .a(_if));   // use partial implicit port connections
	yourDesign	yd0 ( .*, .b(_if));

endmodule

module checker ( interface   chk_if,
                 input logic clk);

	always @ (posedge clk)
		if (chk_if.ack)
			chk_if.gnt <= 1;

endmodule

module tb;
	logic clk = 0;
	myInterface _if;

	checker chk0 ( .*, .chk_if(_if) );
endmodule