SystemVerilog Constraints

When verifying a digital design, one of the core challenges is generating meaningful stimulus — inputs that exercise the design the way it will be used in the real world. SystemVerilog constraints let you define the boundaries of legal behavior and let the simulator's built-in solver figure out what values to generate within those boundaries.

14 min read | Intermediate Level

What You'll Learn

• The difference between direct and randomized tests, and why constrained-random became the dominant verification methodology
• How to declare a constraint, and the difference between rand and randc
• The core constraint expression types: relational, inside, dist, and implication
• How to enable and disable constraints at runtime, and add a one-off constraint without changing the class

Direct Tests vs Randomized Tests

What Are Direct Tests?

A direct test is fully hand-crafted. You explicitly set every signal to every value, in the exact sequence you want:

// Direct test: manually drive a specific transaction
pkt.addr = 8'h10;
pkt.data = 8'hAB;
pkt.cmd  = WRITE;

Direct tests are fast to write for well-understood scenarios and are great for checking a specific known bug. However, they don't scale — a moderately complex design might have hundreds of valid configurations, and writing a direct test for every combination is impractical.

What Are Randomized Tests?

A randomized test relies on the simulator to generate values automatically. The test runs repeatedly with different seeds, so each run exercises a different slice of the design's behavior:

// Randomized test: let the solver pick the values
assert(pkt.randomize());

Over many runs, randomized tests naturally exercise corner cases a human engineer simply wouldn't think to write explicitly — exactly why constrained-random verification is the dominant methodology in modern chip verification, including industry frameworks like UVM. The catch is the word constrained: purely unconstrained randomization is noisy, spending most of your simulation budget on invalid or uninteresting inputs. Constraints are how you guide the randomizer to stay in bounds.

What Is a Constraint?

A constraint narrows the space of valid random values for one or more variables. You define constraints inside a class, alongside the variables they govern. The solver reads every active constraint and picks values that satisfy all of them simultaneously:

class Packet;
    rand bit [7:0] addr;
    rand bit [7:0] data;

    constraint addr_range { addr inside {[8'h00 : 8'h7F]}; }
endclass

• rand keyword: marking a variable rand tells the solver it's a candidate for randomization. Without it, randomize() ignores the variable entirely.
• constraint block: named with a label (addr_range), the body is an expression that must evaluate to true.
• inside operator: restricts addr to the lower half of the 8-bit range.

8'h00 : 8'h7F spans exactly 128 values (0 through 127) out of the 256 possible values an 8-bit field can hold — precisely half the full range, which is why it's described as "the lower half."

The rand and randc Keywords

rand — Uniform Random

Variables declared with rand are assigned uniformly random values within the constraint space on each call to randomize(). Each call is independent — you might get the same value twice in a row:

rand bit [3:0] opcode;   // any value 0-15, independently each time

randc — Random Cyclic

Variables declared with randc cycle through all possible values before repeating any — like drawing cards from a shuffled deck without replacement:

randc bit [3:0] opcode;  // cycles through 0-15 before repeating

randc is particularly useful when you want guaranteed coverage of all values, not just statistically likely coverage — verifying a register address space where every address must be hit is a classic case.

Writing a Constraint Block

Multiple expressions inside one constraint block are treated as a logical AND — all must be satisfied:

class BusTransaction;
    rand bit [7:0]  addr;
    rand bit [31:0] data;
    rand bit [1:0]  burst_len;

    // addr must be 4-byte aligned
    constraint align_addr { addr[1:0] == 2'b00; }

    // burst_len between 1 and 3
    constraint valid_burst { burst_len >= 1; burst_len <= 4; }
endclass

Packet pkt = new();

// Correct: assert will trigger a fatal if randomize fails
assert(pkt.randomize()) else $fatal(1, "Randomization failed!");

constraint impossible { addr > 8'hFF; }  // addr is 8-bit, can never exceed 0xFF

constraint c1 { data < 32'h1000; }
constraint c2 { addr >= 8'h10; addr <= 8'hF0; }

constraint c3 { opcode inside {READ, WRITE, IDLE}; }
constraint c4 { size inside {[4:64]}; }
constraint c5 { !(opcode inside {RESERVED_1, RESERVED_2}); }

constraint cmd_dist {
    cmd dist { READ := 70, WRITE := 30 };
}

// Values 0-7 SHARE a total weight of 10; value 8 gets 50 all to itself
constraint priority_dist {
    priority dist { [0:7] :/ 10, 8 := 50 };
}

constraint read_no_data {
    (cmd == READ) -> (data == 0);
}

pkt.addr_range.constraint_mode(0);  // disable
pkt.addr_range.constraint_mode(1);  // re-enable

assert(pkt.randomize() with { addr == 8'hFF; });

class Frame;
  rand bit [2:0] kind;
  rand bit [7:0] len;

  constraint c_kind_dist {
    kind dist { 0 := 60, 1 := 30, 2 := 10 };
  }

  constraint c_idle_len {
    (kind == 2) -> (len == 0);
  }
endclass