SystemVerilog forever loop

An always or forever block without a delay element will hang the simulation. The simulator only moves time forward when every process is waiting. A loop that never waits keeps running at the same timestamp, and no other process gets a turn.

The difference is where each one may appear:

Because an always block cannot be placed inside a class or another procedural block, class-based testbenches use a forever loop inside a task to get the same effect.

Example: Clock Generation

A free-running clock is the classic use of forever. The loop toggles the clock after every half-period delay.

module tb;
  bit clk;                     // 2-state, starts at 0

  initial begin
    forever #5 clk = ~clk;     // toggle every 5 ns: 10 ns period (100 MHz)
  end

  initial begin
    #50 $finish;               // the clock loop never ends, so stop here
  end
endmodule

The clock rises at 5, 15, 25, 35 and 45 ns. The second initial block is essential: without $finish, the clock would keep the simulation running forever.

Example: A Testbench Monitor

The pseudo code below sketches a testbench monitor. Once started, it keeps running for as long as there is activity on the bus it watches.

class Monitor;
	virtual task run();
		forever begin
			@(posedge vif.clk);
			if (vif.write & vif.sel)
				// Capture write data
			if (!vif.write & vif.sel)
				// Capture read data
		end
	endtask
endclass

module tb;
	Monitor mon = new();

	// Start the monitor task and allow it to continue as
	// long as there is activity on the bus
	initial begin
		fork
			mon.run();
		join_none
	end
endmodule

• @(posedge vif.clk) is the timing control. Each pass samples the bus once per clock and then waits for the next edge.
• fork ... join_none starts run() as a separate process. The initial block can then carry on instead of being stuck inside a task that never returns.

This is pseudo code. Comments are not statements, so as written the second if becomes the body of the first, and the second if has no body at all, which is a compile error. In real code, give each if its own statement or begin ... end block. vif would also need to be declared in the class as a virtual interface handle.

Stopping a forever Loop

A forever loop has no exit condition, so something must end it explicitly:

• $finish ends the whole simulation, as in the clock example.
• break inside the loop exits just that loop, and execution continues after it.
• disable on a named block, or disable fork, stops the loop from another process. See disable fork.

module tb;
  bit clk, done;
  int cycles;

  always #5 clk = ~clk;          // clock rises at 5, 15, 25 ... ns
  initial #73 done = 1;          // some other process signals completion

  initial begin
    forever begin
      @(posedge clk);
      cycles++;
      if (done) break;           // leave the loop on the first edge after done
    end
    // Runs only after break: prints "Loop exited after 8 cycles at 75"
    $display ("Loop exited after %0d cycles at %0t", cycles, $time);
    $finish;
  end
endmodule

done goes high at 73 ns. The loop sees it on the next rising edge at 75 ns, which is the eighth edge, and break hands control to the $display after the loop.

forever in Digital Design

forever is a verification-only construct, and mainstream synthesis tools do not accept it in RTL. Hardware that "runs forever" is described with always_ff for clocked logic and always_comb for combinational logic (see always_comb and always_ff). Design engineers still use forever in their own block-level testbenches to generate clocks and apply stimulus.

Common Beginner Mistakes

`timescale 1ns/1ps
module tb;
  bit clk;

  initial forever #2.5 clk = ~clk;   // 2.5 ns half period = 5 ns period (200 MHz)

  initial begin
    repeat (20) @(posedge clk);       // count 20 rising edges
    $finish;                          // 20th edge is at 2.5 + 19*5 = 97.5 ns
  end
endmodule