SystemVerilog Covergroup and Coverpoint

Functional coverage is built from two closely related pieces: coverpoint, which does the actual work of tracking what's been exercised, and covergroup, which is the container that holds one or more coverpoints together. This article starts with the coverpoint, since that's the piece that actually answers the "have we tested everything?" question, then shows how covergroups bring several of them together into one coverage model.

8 min read | Intermediate Level

What You'll Learn

• What a coverpoint is and why it's the fundamental unit of functional coverage
• How to declare a coverpoint, and how its legal values get grouped into bins
• What a covergroup is and how it brings multiple coverpoints together
• How a covergroup gets sampled, and how to read its reported coverage percentage

What Is a Coverpoint, and Why Does It Matter?

A coverpoint watches a single integral variable or expression and records which of its legal values have actually occurred during the test. Every time it's sampled, a coverpoint checks the current value of whatever it's watching and marks that value as "hit."

This is the piece that does the real measuring in functional coverage — it's the difference between assuming your random stimulus was thorough and actually knowing it was. Each value (or group of values) a coverpoint tracks lives in a bin. By default, SystemVerilog automatically creates one bin per legal value of the variable being covered — a 2-bit variable gets 4 automatic bins, one per possible value. SystemVerilog Coverpoint Bins covers how to group values into custom bins yourself, which matters once a variable is too wide for one bin per value to be practical.

How a Coverpoint Is Written

A coverpoint can optionally be given a name (a label) before a colon:

[label :] coverpoint <variable_or_expression>;

Parameters:

• label — an optional name for the coverpoint, followed by a colon
• variable_or_expression — the signal, bit-slice, or expression the coverpoint tracks

A coverpoint never appears on its own, though — it always lives inside a covergroup, which is the container for the overall coverage model.

What Is a Covergroup?

A covergroup is a user-defined type that encapsulates a coverage model — it can be defined once and instantiated multiple times through its new() function, just like a class. A covergroup can be defined inside a package, module, program, interface, or class, and typically brings together:

• One or more coverpoints — the individual signals or expressions being tracked
• Cross coverage between coverage points — tracking combinations of values across two or more coverpoints, rather than each one in isolation (covered in its own article later in this chapter)
• An event that defines when the covergroup is sampled — a clock edge or any other SystemVerilog event, deciding how often every coverpoint inside it checks its current value
• Other options to configure the coverage object — things like per-coverpoint weight or a target coverage goal

How a Covergroup Is Written

A minimal covergroup declaration wraps one or more coverpoints between covergroup and endgroup:

covergroup <covergroup_name> [(arguments)] [@ (sampling_event)];
	[label :] coverpoint <variable_or_expression>;
	...
endgroup

// Instantiate the covergroup, similar to instantiating a class
<covergroup_name> <instance_name> = new();

Parameters:

• <covergroup_name> — the name of the covergroup type being defined
• (arguments) — optional arguments passed in when the covergroup is instantiated (optional)
• @ (sampling_event) — the event that triggers sampling, such as a clock edge (optional, but almost always used)

A Single Coverpoint in Action

Here's that skeleton filled in with a minimal working example — one covergroup with one coverpoint tracking the variable mode. The group is sampled on every posedge clk, while mode and cfg are assigned fresh random values on every negedge clk — so by the time each sample happens, mode already holds that cycle's random value:

module tb;
  
  // Declare some variables that can be "sampled" in the covergroup
  bit [1:0] mode;
  bit [2:0] cfg;
  
  // Declare a clock to act as an event that can be used to sample
  // coverage points within the covergroup
  bit clk;
  always #20 clk = ~clk;
  
  // "cg" is a covergroup that is sampled at every posedge clk
  covergroup cg @ (posedge clk);
    coverpoint mode;
  endgroup
  
  // Create an instance of the covergroup
  cg  cg_inst;
  
  initial begin
    // Instantiate the covergroup object similar to a class object
    cg_inst= new();
  
    // Stimulus : Simply assign random values to the coverage variables
    // so that different values can be sampled by the covergroup object
    for (int i = 0; i < 5; i++) begin
      @(negedge clk);
      mode = $random;
      cfg  = $random;
      $display ("[%0t] mode=0x%0h cfg=0x%0h", $time, mode, cfg);
    end
  end
  
  // At the end of 500ns, terminate test and print collected coverage
  initial begin
    #500 $display ("Coverage = %0.2f %%", cg_inst.get_inst_coverage());
    $finish;
  end
endmodule

Output

ncsim> run
[40] mode=0x0 cfg=0x1
[80] mode=0x1 cfg=0x3
[120] mode=0x1 cfg=0x5
[160] mode=0x1 cfg=0x2
[200] mode=0x1 cfg=0x5
Coverage = 50.00 %
Simulation complete via $finish(1) at time 500 NS + 0

mode is 2 bits wide, so it has 4 legal values (0 through 3), and by default a coverpoint creates one automatic bin per legal value, as described earlier. Across the 5 samples shown, only 0x0 and 0x1 ever appeared — 2 out of 4 possible values — which is exactly why get_inst_coverage() reports 50.00%.

Multiple Coverpoints in One Covergroup

A covergroup can contain more than one coverpoint, and each one can optionally be given a name followed by a colon. mode can take any value from 0 to 3, and cfg can take any value from 0 to 7 — the question functional coverage answers is: out of all the values each of these could legally take, how many actually showed up during the test?

module tb;
  
  bit [1:0] mode;
  bit [2:0] cfg;
  
  bit clk;
  always #20 clk = ~clk;
  
  // "cg" is a covergroup that is sampled at every posedge clk
  // This covergroup has two coverage points, one to cover "mode"
  // and the other to cover "cfg". Mode can take any value from
  // 0 -> 3 and cfg can take any value from 0 -> 7
  covergroup cg @ (posedge clk);
  
    // Coverpoints can optionally have a name before a colon ":"
    cp_mode    : coverpoint mode;
    cp_cfg_10  : coverpoint cfg[1:0];
    cp_cfg_lsb : coverpoint cfg[0];
    cp_sum     : coverpoint (mode + cfg);
  endgroup
  
  cg  cg_inst;
  
  initial begin
    cg_inst= new();

    for (int i = 0; i < 5; i++) begin
      @(negedge clk);
      mode = $random;
      cfg  = $random;
      $display ("[%0t] mode=0x%0h cfg=0x%0h", $time, mode, cfg);
    end
  end
  
  initial begin
    #500 $display ("Coverage = %0.2f %%", cg_inst.get_inst_coverage());
    $finish;
  end
endmodule

Output

ncsim> run
[40] mode=0x0 cfg=0x1
[80] mode=0x1 cfg=0x3
[120] mode=0x1 cfg=0x5
[160] mode=0x1 cfg=0x2
[200] mode=0x1 cfg=0x5
Coverage = 68.75 %
Simulation complete via $finish(1) at time 500 NS + 0

Note that a coverpoint doesn't have to track a plain variable — cp_cfg_10 covers a bit-slice (cfg[1:0]), cp_cfg_lsb covers a single bit (cfg[0]), and cp_sum covers an entire expression (mode + cfg). get_inst_coverage() reports the overall coverage across all four coverpoints combined, which is why the second run's 68.75% differs from the single-coverpoint example's 50.00% — it's now an aggregate across every coverpoint in the group.

Common Beginner Mistakes

covergroup cg @ (posedge clk);
  coverpoint mode;
  coverpoint cfg;
endgroup