SystemVerilog Interface Parameters

An interface can be parameterized the same way a module can — letting the same interface definition adapt its signal widths, depths, or other configuration to whatever design it's connected to, instead of writing a separate interface for every bus width you need to support.

6 min read | Intermediate Level

What You'll Learn

• The basic syntax for declaring a parameter on an interface
• How to override a parameter's default value at instantiation
• How to connect a parameterized interface to a design that shares the same parameter
• What happens when an interface's parameter and a design's parameter don't match

Basic Syntax

A parameter is declared the same way you would for a module — between #( and ), right after the interface name:

interface myBus #(parameter D_WIDTH=31) (input clk);
	logic [D_WIDTH-1:0] data;
	logic               enable;
endinterface

D_WIDTH defaults to 31 here, so data ([D_WIDTH-1:0], or [30:0]) is 31 bits wide unless something overrides it.

Overriding the Default at Instantiation

Just like a module, an interface's parameter is overridden with #(...) at the point of instantiation:

module tb;
	logic clk;

	// Uses the default: D_WIDTH = 31, so data is 31 bits wide
	myBus bus_default (clk);

	// Overrides D_WIDTH to 8, so data is only 8 bits wide
	myBus #(.D_WIDTH(8)) bus_narrow (clk);
endmodule

bus_default keeps the interface's own default of 31, giving it a 31-bit data signal. bus_narrow overrides D_WIDTH to 8, shrinking data down to 8 bits — the same interface definition, sized two different ways in two different instances.

Connecting a Parameterized Interface to a Design

The design that uses the interface typically declares a matching parameter of its own, so both sides agree on the width being used:

module bus_slave #(parameter D_WIDTH = 31) (myBus.slave bus_if);
  logic [D_WIDTH-1:0] captured_data;

  always @ (posedge bus_if.clk)
    if (bus_if.enable)
      captured_data <= bus_if.data;
endmodule

module d_top;
	logic clk;

	// Both the interface and the design agree on an 8-bit width
	myBus      #(.D_WIDTH(8)) bus_if (clk);
	bus_slave  #(.D_WIDTH(8)) slave0 (bus_if);
endmodule

Here, both bus_if and slave0 are instantiated with D_WIDTH(8), so captured_data inside bus_slave is declared the same width as bus_if.data — 8 bits, matching on both sides.

interface myBus #(parameter D_WIDTH=31, parameter ADDR_WIDTH=16) (input clk);
	logic [D_WIDTH-1:0]    data;
	logic [ADDR_WIDTH-1:0] addr;
	logic                  enable;
endinterface

module tb;
	logic clk;

	// D_WIDTH overridden to 8 (8-bit data); ADDR_WIDTH left at its default of 16 (16-bit addr)
	myBus #(.D_WIDTH(8)) bus_if (clk);
endmodule