SystemVerilog Parameterized Classes

At times it's much easier to write a generic class that can be instantiated in multiple ways to achieve different array sizes or data types. This avoids rewriting nearly-identical code for specific features like size or type, letting a single specification serve many different objects instead — achieved by extending SystemVerilog's parameter mechanism to classes.

Parameters are like constants local to the specified class. Classes are allowed a default value for each parameter, which can be overridden at instantiation.

9 min read | Intermediate Level

What You'll Learn

• Why parameterizing a class avoids rewriting nearly-identical code for different sizes or types
• How to override a class parameter's value, or its entire data type, at instantiation
• How the same parameter mechanism controls a value's size in one case, and a completely different data type in another
• Why assigning a value into a narrower parameterized type silently truncates it, rather than raising an error

Syntax

// Declare parameterized class
class  #();
class Trans #(addr = 32);

// Override class parameter
  #() ;
Trans #(.addr(16)) obj;

Parameterizing a Value (Size)

Here, size is the parameter, defaulting to 8, and controls how wide the out property is:

// A class is parameterized by #()
// Here, we define a parameter called "size" and gives it
// a default value of 8. The "size" parameter is used to
// define the size of the "out" variable
class something #(int size = 8);
	bit [size-1:0] out;
endclass

module tb;
  
  // Override default value of 8 with the given values in #()
  something  #(16) sth1;                 // pass 16 as "size" to this class object
  something  #(.size (8)) sth2;          // pass 8 as "size" to this class object
  typedef something #(4) td_nibble;      // create an alias for a class with "size" = 4 as "nibble"
  td_nibble nibble;
  
  initial begin
    // 1. Instantiate class objects
    sth1 = new;
    sth2 = new;
  	nibble = new;  
  
    // 2. Print size of "out" variable. $bits() system task will return
    // the number of bits in a given variable
    $display ("sth1.out   = %0d bits", $bits(sth1.out));
    $display ("sth2.out   = %0d bits", $bits(sth2.out));
    $display ("nibble.out = %0d bits", $bits(nibble.out));
  end
endmodule

Output

ncsim> run
sth1.out   = 16 bits
sth2.out   = 8 bits
nibble.out = 4 bits
ncsim: *W,RNQUIE: Simulation is complete.

Note that sth2 explicitly restates the default value (8), showing the two equivalent ways of overriding a parameter: positional (#(16)) or named (#(.size(8))). td_nibble shows a third pattern — using typedef to give a specific parameterization of the class its own convenient name.

Parameterizing a Data Type

Instead of parameterizing a specific value, a class can parameterize an entire data type, using the type keyword:

// "T" is a parameter that is set to have a default value of "int"
// Hence "items" will be "int" by default
class stack #(type T = int);
  T item;  

  function T add_a (T a);
    return item + a;
  endfunction
endclass

module tb;
	stack 			 	st; 	// st.item is by default of int type
	stack #(bit[3:0]) 	bs; 	// bs.item will become a 4-bit vector
	stack #(real) 		rs; 	// rs.item will become a real number
  
  	initial begin
      st = new;
      bs = new;
      rs = new;
  
      // Assign different values, and add 10 to these values
      // Then print the result - Note the different values printed
      // that are affected by change in data type
      st.item = -456;
      $display ("st.item = %0d", st.add_a (10));
  
      bs.item = 8'hA1;
      $display ("bs.item = %0d", bs.add_a (10));
  
      rs.item = 3.14;
      $display ("rs.item = %0.2f", rs.add_a (10));
    end
endmodule

Any type can be supplied as a parameter here, including a user-defined type such as a class or struct.

Output

ncsim> run
st.item = -446
bs.item = 11
rs.item = 13.14
ncsim: *W,RNQUIE: Simulation is complete.

Each line here actually prints the return value of add_a(10), not the object's item property directly — the label just happens to say "item" for readability. bs is the interesting one to trace through: T is bit[3:0] (4 bits, range 0–15), so assigning 8'hA1 (161 decimal) into bs.item truncates it down to just the lower 4 bits — 0x1 — before anything else happens. add_a(10) then computes 1 + 10 = 11, which fits comfortably within 4 bits, matching the printed 11.

Common Beginner Mistakes

class Buffer #(type T = int, int depth = 4);
  T data [depth];
endclass

module tb;
  Buffer            b1;   // defaults: int, depth=4
  Buffer #(byte, 2) b2;   // byte, depth=2

  initial begin
    b1 = new;
    b2 = new;

    $display ("b1 data = %0d bits", $bits(b1.data));
    $display ("b2 data = %0d bits", $bits(b2.data));
  end
endmodule