Using Display Statements Effectively

A $monitor that watches a fast-toggling signal like clk will print a new line every half-period for the entire simulation, producing a log file that can reach gigabytes in size and becomes impossible to read. Only monitor signals that change infrequently, or use $monitoroff during clock-heavy setup phases.

Choosing Between Them

A simple rule covers most situations:

• Use $display for messages tied to execution flow — branch confirmations, transaction start/end markers, values after blocking assignments.
• Use $strobe for printing signal values in clocked blocks — whenever the signal is updated by a non-blocking assignment in the same or a concurrent block.
• Use $monitor for continuous tracing of a small, slowly-changing set of signals across the entire simulation — typically during initial bring-up of a new design.

There is also $write, which is identical to $display but does not append a newline. Use it when you want to build a line incrementally across multiple calls — for example, printing a bus byte by byte in a loop before finishing with $display("") to flush the newline.

$time, $realtime, and $stime

Every log message should include a timestamp so you can correlate it with the waveform. SystemVerilog provides three variants:

• $time — returns the current simulation time as a 64-bit integer in the time units declared by the `timescale directive. This is the right choice in most cases. Print it with the %0t format specifier.
• $realtime — returns the current simulation time as a real number, preserving fractional time. Useful when your design uses a timescale with fine precision (e.g. `timescale 1ns/1ps) and you need to log sub-unit events accurately.
• $stime — a 32-bit unsigned integer version of $time. It wraps around at 2³² time units, making it unsafe for long simulations. Avoid it unless you have a specific reason.

`timescale 1ns/1ps

initial begin
    #10.5;
    $display("$time    = %0t",  $time);     // prints: 10  (truncated to integer ns)
    $display("$realtime = %0t", $realtime);  // prints: 10.5 (preserves fraction)
    $display("$stime   = %0d",  $stime);     // prints: 10  (32-bit integer)
end

Always use $time with %0t rather than %d. The %t specifier respects the `timescale unit and prints the time with the correct unit suffix when used with $timeformat. Using %d just prints a raw integer with no unit context.

Format Specifiers

All three tasks use the same format string syntax. The format string can contain literal text, escape sequences, and format specifiers starting with %:

Common escape sequences in the format string: \n inserts a newline (useful with $write), \t inserts a tab for column alignment, and %% prints a literal percent sign.

Writing Structured Log Output

A log file that is easy to grep and parse saves significant debug time. A few consistent conventions make a large difference:

// Consistent timestamp prefix on every line
$display("[%0t] WRITE addr=0x%h data=0x%h", $time, addr, wdata);
$display("[%0t] READ  addr=0x%h data=0x%h", $time, addr, rdata);

// Severity tags for filtering
$display("[%0t] ERROR: data mismatch — exp=0x%h got=0x%h", $time, exp, got);
$display("[%0t] INFO:  reset deasserted", $time);

// Aligned columns using tab stops
$display("[%0t]\taddr=%0h\tdata=%0h\tbe=%b", $time, addr, data, be);

With a consistent [time] prefix, you can quickly find all messages at a specific timestep with a simple text search. Severity tags (ERROR, WARN, INFO) let you filter the log down to just failures when running regression. Column alignment makes bus values easy to compare across multiple lines.

Common Mistakes

`timescale 1ns/1ps

module tb;
    reg clk, rst_n, valid;
    reg [7:0] data;

    // Clock generation
    initial clk = 0;
    always #5 clk = ~clk;

    // Monitor — logs every signal change
    initial
        $monitor("clk=%b rst=%b valid=%b data=%h", clk, rst_n, valid, data);

    // Stimulus
    initial begin
        rst_n = 0; valid = 0; data = 8'h00;
        #12 rst_n = 1;
        @(posedge clk);
        data  <= 8'hA5;        // non-blocking
        valid <= 1;
        $display("sent: data=%h valid=%b", data, valid);  // check values
    end
endmodule

// Fixed monitor — no clk, includes timestamp
initial
    $monitor("[%0t] rst=%b valid=%b data=%h", $time, rst_n, valid, data);

// Fixed display — use $strobe, include timestamp
@(posedge clk);
data  <= 8'hA5;
valid <= 1;
$strobe("[%0t] sent: data=%h valid=%b", $time, data, valid);