Statement coverage is a type of code coverage that measures the percentage of code statements executed during the simulation. Here's an example of statement coverage RTL code:
module counter(input clk, input reset, output reg [7:0] count); always @(posedge clk) begin if(reset) begin count <= 8'h00; end else begin count <= count + 1; end end endmodule
In this example, the counter module counts up every time the input clock signal goes high, unless the reset signal is also high. To determine statement coverage, a testbench would need to be created that stimulates each line of code in the module.
Here's an example of a SystemVerilog testbench that could be used to achieve statement coverage:
module counter_tb(); reg clk = 0; reg reset = 0; wire [7:0] count; counter dut(clk, reset, count); initial begin $monitor("Count = %h", count); reset = 1; #10; reset = 0; end always #5 clk = ~clk; endmodule
In this testbench, the reset signal is
initially set high to clear the counter. The monitor task displays the current count value in the console every time it changes. The always block toggles the clock signal every five units of time.
Running this testbench would stimulate each line of code in the counter module, thus achieving 100% statement coverage. If test cases were added that didn't stimulate each line of code in the module, the statement coverage percentage would decrease accordingly.