An I2C bus can have more than one controller. Two of them may decide to start a transaction at the same moment, and there is no arbiter to choose between them. I2C resolves this on the wires themselves, using the open-drain lines: clock synchronization merges the two clocks, and bit-by-bit arbitration on SDA decides the winner without corrupting its data. This article shows arbitration in a simulation, then looks briefly at two relatives of I2C: SMBus and I3C.
8 min read | Intermediate
What You'll Learn
- Explain clock synchronization between controllers
- Follow bit-by-bit arbitration on SDA
- Handle a lost arbitration correctly in a controller
- Compare I2C with SMBus and I3C
Clock Synchronization
Each controller drives its own SCL, but the line is a wired-AND: it is low as long as any controller pulls it low. When SCL falls, every controller starts counting its low period. A controller that finishes early releases SCL, sees it still low, and waits. The line goes high only when the controller with the longest low period lets go; then all of them count their high period, and the first to finish pulls SCL low again. The result is one shared clock, with the low time of the slowest controller and the high time of the fastest. It is the same mechanism a target uses for clock stretching.
Arbitration on SDA
A controller may only start when the bus is free, but two can start within the hold time of a START and both believe they own the bus. They then both send their address byte. While SCL is high, each controller compares SDA with what it is sending. As long as they send the same bits, nothing happens. At the first bit where one sends 1 (releases SDA) and the other sends 0 (pulls SDA low), the line is low: the controller that sent 1 sees a 0, knows it has lost, and stops driving SDA. The winner never notices; the bus carried exactly what it sent.
In the example, controller A writes to target 0x50 and controller B to 0x51, starting in the same clock cycle:
1725 controller B lost arbitration, waits for STOP 6015 controller A: write 0x50 reg1 = 0xa7 12105 controller B: write 0x51 reg1 = 0x3c 20115 read 0x50 reg1 = 0xa7 28125 read 0x51 reg1 = 0x3c
0x50 and 0x51 differ only in the last address bit: A sends 0 and B sends 1. B detects the loss at the end of that bit, releases SDA, and waits for A's STOP before trying again. Both writes complete, A's first. Because a 0 always wins, the controller addressing the lower address wins when two transactions collide in the address byte; if both address the same target, arbitration continues into the data bytes.
In the controller, the check is one condition at the end of every bit's high time:
if (op == WRITE && bitn < 8 && out_bit && !sda_i) begin
arb_lost <= 1'b1; // we sent 1 but the bus is 0: lost
sda_oe <= 1'b0;
scl_oe <= 1'b0;
busy <= 1'b0;
done <= 1'b1;
end
Quick Check
Q: Two controllers send exactly the same transaction at the same time. What happens?
Show Answer
Neither ever sees a mismatch, so both complete the transaction, and the target receives it once. The specification notes that two controllers can complete an entire transaction this way without error.
What the Loser Must Do
- stop driving SDA at once, but may keep generating clock pulses until the end of the byte;
- if it can also be a target, switch to target mode immediately, because the winner might be addressing it;
- wait until the bus is free (after a STOP) and restart its transaction from the beginning.
The specification also lists undefined situations, such as one controller sending a repeated START or STOP while the other is still sending data. Multi-controller systems avoid them by having controllers use the same transaction formats.
SMBus
The System Management Bus, developed by Intel and others in 1995 and found in most PCs, uses I2C hardware and addressing with some changes:
- the clock runs between 10 kHz and 100 kHz in the original versions, and devices may time out if a transaction takes too long: a target may not hold SCL low longer than 35 ms;
- fixed logic thresholds (low below 0.8 V, high above 2.1 V) instead of fractions of the supply;
- defined command formats, an Address Resolution Protocol for dynamic addresses, and optional packet error checking.
An SMBus controller can talk to I2C devices and the other way round, as long as the clock and timeout rules are respected.
I3C
I3C, from the MIPI Alliance (2017), is the successor to I2C for sensors in phones and other devices. It keeps the two wires and is backward compatible with I2C targets, but it uses push-pull drivers for data when possible, reaching much higher speeds at lower power. It adds dynamic address assignment and in-band interrupts, so targets can signal the controller without an extra interrupt wire. The current I2C specification adopted I3C's controller and target terminology.
Quick Check
Q: An I2C target needs 50 ms to complete an internal write and stretches SCL for that time. Can it be used on an SMBus?
Show Answer
No. SMBus limits clock stretching to 35 ms; after that, devices time out and reset the transaction. I2C itself sets no limit.
Running It in ChipVerify Lab
The example contains two controllers, two targets and the arbitration test. Change the addresses and see who wins.
Common Mistakes
Mistake #1: Treating lost arbitration as a NACK
A controller that reports "no ACK" after losing arbitration gives up on a transaction that would have succeeded. Check the arbitration flag and retry.
Mistake #2: Starting while the bus is busy
Arbitration only resolves simultaneous starts. A controller must watch for START and STOP and never begin while another transaction is in progress.
Mistake #3: Push-pull SCL in a multi-controller system
Clock synchronization relies on the wired-AND of SCL. A push-pull clock fights the other controller's clock.
Practice Exercise
Challenge: Swap the Addresses
Let controller A write to 0x51 and controller B to 0x50. Controller A's write_reg task only checks the ACK, not arb_lost. Predict what it reports and what ends up in target 0x51.
Hint
A now sends the 1 in the last address bit.
Solution
1955 write 0x51: no ACK (NACK) 6015 controller B: write 0x50 reg1 = 0x3c 14025 read 0x50 reg1 = 0x3c 22035 read 0x51 reg1 = 0x00
A loses the arbitration, but its task does not look at arb_lost; it sees no valid ACK, reports a NACK and gives up. B's write succeeds, and register 1 of target 0x51 stays at 0x00. The fix is in the driver: after a lost arbitration, wait for the STOP and retry, as controller B's task does.
Open the ready-made example in the lab and run the simulation.
Summary
- Several controllers can share an I2C bus; there is no central arbiter.
- Clock synchronization on the wired-AND SCL merges their clocks.
- Arbitration happens bit by bit: a controller that sends 1 but sees 0 has lost, and stops driving.
- The winner's transfer is never corrupted; the loser retries after the STOP.
- SMBus adds timeouts, fixed levels and command formats; I3C adds speed, dynamic addressing and in-band interrupts.
