An AXI read transaction uses two channels. The master sends the address and burst description on AR, and the slave returns the data on R, one beat per handshake, each beat with its own response. Because the master can send several read addresses before any data comes back, reads are where AXI's outstanding transactions pay off most. This article follows read bursts through a simulation, including a master that stalls the data.
8 min read | Intermediate
What You'll Learn
- Describe the signals of the AR and R channels
- Follow several read transactions in flight at once
- Use
RREADYto apply backpressure on read data - Handle a response on every read beat
The Read Address Channel (AR)
The AR channel has the same fields as AW: ARID, ARADDR, ARLEN, ARSIZE, ARBURST, ARLOCK, ARCACHE, ARPROT and the optional ARQOS, ARREGION and ARUSER, with ARVALID and ARREADY. One handshake describes a burst of ARLEN + 1 beats.
The Read Data Channel (R)
| Signal | Meaning |
|---|---|
| RID | The ARID of the transaction this beat belongs to |
| RDATA | Read data |
| RRESP[1:0] | Response for this beat: OKAY, EXOKAY, SLVERR or DECERR |
| RLAST | High on the last beat of the burst |
| RUSER | Optional user-defined information |
| RVALID, RREADY | Handshake |
Unlike writes, a read has no separate response channel. Each beat carries its own RRESP, so a slave can report an error on one beat and OKAY on the others. The read is complete when the master has received the beat with RLAST.
The rules from The Five Channels and the VALID/READY Rules apply: the slave raises RVALID only after the address handshake, and must not wait for RREADY to do so. Even a slave with only one possible source of data may only assert RVALID in response to a request.
Quick Check
Q: A read burst of 8 beats hits an error on beat 3. How many beats does the slave send?
Show Answer
All 8. AXI has no early termination: the slave must complete the burst, and it marks the failing beats with SLVERR (or DECERR) in RRESP.
Two Reads in Flight
The master first fills eight words at 0x300, then issues two four-beat reads with IDs 3 and 4 on consecutive cycles. Its RREADY is low for two cycles in the middle of the data. The slave has a read latency of three cycles and queues the second address while the first burst is in progress.
read(3, 12'h300, 3, WORD, INCR, 0, 12); // 4 beats
read(4, 12'h310, 3, WORD, INCR, 0, 0); // 4 more, issued straight after
rready_pat = 32'hFFF9FFFF; // RREADY low in cycles 17 and 18
145 AR id=3 addr=0x300 len=3 size=4 INCR 155 AR id=4 addr=0x310 len=3 size=4 INCR 175 R id=3 data=0x00000030 OKAY 185 R id=3 data=0x00000031 OKAY 215 R id=3 data=0x00000032 OKAY 225 R id=3 data=0x00000033 OKAY last 235 R id=4 data=0x00000034 OKAY 245 R id=4 data=0x00000035 OKAY 255 R id=4 data=0x00000036 OKAY 265 R id=4 data=0x00000037 OKAY last
Both addresses are accepted before the first beat returns: two transactions in flight. The data comes back one beat per cycle except where the master holds RREADY low; there the slave keeps RVALID high and RDATA stable (0x32 waits two cycles). The beats of ID 4 follow straight after the last beat of ID 3, because its latency already elapsed while the first burst was transferring.
This slave answers in order, so the data of ID 4 can only follow ID 3. A slave that answers out of order is shown in Transaction IDs and Ordering.
Inside the Slave
The read side keeps a queue of up to four addresses, each stamped with the cycle when its data may go out. The head of the queue starts sending when its time has come and the previous burst is on its last beat:
wire present = r_active && (!RVALID || RREADY); // a new beat can go out this cycle
wire can_load = q_count != 3'd0 && cycle >= q_time[q_head] &&
(!r_active || (present && r_left == 8'd0));
if (present) begin
RVALID <= 1'b1;
RID <= r_id;
RLAST <= (r_left == 8'd0);
RDATA <= mem[r_addr[11:2]];
// RRESP: OKAY, EXOKAY or SLVERR
r_addr <= next_addr(r_addr, r_size, r_burst, r_len);
end
The condition !RVALID || RREADY is the core of every AXI sender: a new beat may be placed on the channel when the channel is empty or when the current beat is being taken in this cycle.
Quick Check
Q: Why does the slave update RDATA only when !RVALID || RREADY is true?
Show Answer
Because once RVALID is high the beat must stay stable until the master takes it. Changing RDATA while RVALID is high and RREADY is low would replace a beat the master has not received.
Running It in ChipVerify Lab
The example runs these two reads. Change rready_pat to stall other beats and watch the slave hold its data.
Common Mistakes
Mistake #1: Ignoring RRESP on all but the last beat
Every read beat has its own response. A master that only checks the last beat can use data from a failed beat.
Mistake #2: Stopping a burst early
A master that needs fewer beats must still accept all of them; it may discard the extra data. For a read-sensitive device such as a FIFO, it must request exactly the right length.
Mistake #3: RVALID that waits for RREADY
A slave must present read data without waiting for RREADY. Waiting can deadlock against a master that waits for RVALID, which it is allowed to do.
Practice Exercise
Challenge: One Read at a Time
Set max_reads = 1; before the two reads. When is the second address sent now, and when does its last beat arrive?
Hint
With one read in flight, the master waits for RLAST of the first read before it sends the next address, and the second read pays its full latency.
Solution
145 AR id=3 addr=0x300 len=3 size=4 INCR 175 R id=3 data=0x00000030 OKAY 185 R id=3 data=0x00000031 OKAY 215 R id=3 data=0x00000032 OKAY 225 R id=3 data=0x00000033 OKAY last 235 AR id=4 addr=0x310 len=3 size=4 INCR 265 R id=4 data=0x00000034 OKAY 275 R id=4 data=0x00000035 OKAY 285 R id=4 data=0x00000036 OKAY 295 R id=4 data=0x00000037 OKAY last
The second address leaves at 235 ns, after the first RLAST, and the read ends at 295 ns instead of 265 ns: the three-cycle latency is now paid twice.
Open the ready-made example in the lab and run the simulation.
Summary
- A read uses AR for the burst description and R for the data beats.
- Every R beat carries
RID,RRESPand, on the last one,RLAST. - The slave must send all beats of a burst, even after an error.
- The master applies backpressure with
RREADY; the slave holds the beat meanwhile. - Several read addresses can be in flight, which hides the slave's latency.
