AHB Transfers and Pipelining

Every AHB transfer has two phases: an address phase that lasts one cycle, and a data phase that lasts one or more. The trick that makes AHB fast is that the two phases of different transfers overlap: while one transfer moves its data, the next one is already presenting its address. This article follows single transfers, then back-to-back transfers, and shows what a wait state does to the pipeline.

8 min read | Intermediate

What You'll Learn

• Identify the address phase and the data phase of an AHB transfer
• Explain how back-to-back transfers overlap in the pipeline
• Predict how a wait state stretches two transfers at once
• Drive pipelined AHB transfers from a testbench

A Single Write and a Single Read

In the address phase, the master drives HADDR, HWRITE, HSIZE, HBURST and HTRANS = NONSEQ (a single transfer, or the first of a burst). The slave samples them at the end of that cycle. In the data phase, the master drives HWDATA for a write, or the slave drives HRDATA for a read, and the slave answers with HREADY and HRESP.

A slave cannot stretch the address phase of its own transfer. Every slave must be able to sample the address in that one cycle. It can only stretch the data phase, by driving HREADYOUT low.

Back-to-Back Transfers

Nothing stops the master from putting the next address on the bus during the data phase of the current transfer. That is the normal case. This testbench runs two writes and two reads back to back, into a memory slave with no wait states:

burst(1, SINGLE, 32'h020, WORD, 1, 32'hB1);   // write 0x20
burst(1, SINGLE, 32'h024, WORD, 1, 32'hB2);   // write 0x24
burst(0, SINGLE, 32'h020, WORD, 1, 0);        // read 0x20
burst(0, SINGLE, 32'h024, WORD, 1, 0);        // read 0x24

75  write 0x0020 = 0x000000b1  OKAY
85  write 0x0024 = 0x000000b2  OKAY
95  read  0x0020 = 0x000000b1  OKAY
105  read  0x0024 = 0x000000b2  OKAY

A transfer completes every 10 ns, one per cycle. Each transfer still takes two cycles from address to data, but because the phases overlap, four transfers take five cycles instead of eight. Compare that with APB, where each transfer needs at least two cycles of its own.

The Master in the Testbench

A pipelined master is easiest to write as an engine that walks through a list of address phases. It keeps two indexes: ap, the command in the address phase, and dp, the command in the data phase. At every rising edge where HREADY is high, both move forward by one:

// Address phase outputs come from the command at index ap
assign HTRANS = (HRESETn && ap < n && !skip) ? c_trans[ap] : IDLE;
assign HADDR  = (ap < n) ? c_addr[ap] : c_addr[n-1];
// ... HWRITE, HSIZE and HBURST the same way ...

// Data phase output comes from the command at index dp
assign HWDATA = (dp >= 0 && c_write[dp]) ? c_wdata[dp] : 32'h0;

always @(posedge HCLK) begin
  if (HRESETn) begin
    if (HREADY) begin
      // the data phase of command dp completes here (log or check it)
      dp <= (ap < n) ? ap : -1;          // the address phase moves into the data phase
      if (ap < n)
        ap <= ap + 1;                    // and the next command takes the address phase
    end
  end
end

The burst task fills the list. When HREADY is low, nothing moves: the address phase of ap and the data phase of dp are both held, exactly as the protocol requires.

A Wait State Stretches Two Transfers

Now the same four transfers go to a slave that inserts one wait state on every transfer:

45  write 0x0020 = 0x000000b1  OKAY
65  write 0x0024 = 0x000000b2  OKAY
85  read  0x0020 = 0x000000b1  OKAY
105  read  0x0024 = 0x000000b2  OKAY

Each transfer now completes every 20 ns. Look at what HREADY low does. It extends the data phase of the transfer in progress, and because the next transfer cannot start its data phase yet, its address phase is extended too: 0x24 stays on HADDR for two cycles. The specification says it directly: the address phase lasts one cycle unless it is extended by the previous transfer.

Two rules about data during a wait:

• For a write, the master holds HWDATA valid through every waited cycle.
• For a read, the slave only has to drive valid HRDATA in the last cycle, when HREADY is high.

Running It in ChipVerify Lab

The example contains the memory slave and the command-list master running single and back-to-back transfers. Find the cycle where the address of one transfer and the data of another share the bus.

Common Mistakes

55  write 0x0020 = 0x000000b1  OKAY
85  write 0x0024 = 0x000000b2  OKAY
115  read  0x0020 = 0x000000b1  OKAY
145  read  0x0024 = 0x000000b2  OKAY