Bus Protocols Interview Questions

What is the VALID/READY handshake, and what is its key rule?

A transfer happens on a clock edge where both VALID and READY are high. The source drives VALID when it has data, and the destination drives READY when it can accept data. Either side can wait for the other, which gives back-pressure in both directions.

The key rule is that once VALID is asserted, the source must keep VALID high and hold the data stable until the handshake completes. VALID must also not wait for READY, otherwise two components that each wait for the other can deadlock. READY is allowed to depend on VALID.

Read more on Handshakes.

What are the phases of an APB transfer, and why does it take at least two cycles?

Every APB transfer has a setup phase and an access phase. In the setup phase the master asserts PSEL with the address, direction and write data, while PENABLE is low. In the next cycle it asserts PENABLE, which starts the access phase. The transfer completes when PREADY is high in the access phase.

Because the access phase always follows a separate setup phase, the minimum is two cycles per transfer, and a slave can add wait states by holding PREADY low. This keeps slaves very simple, at the cost of bandwidth, which is why APB is used for low-speed peripheral registers.

Read more on AMBA APB Protocol.

When is PSLVERR valid, and what does it mean?

PSLVERR is only valid in the last cycle of an APB transfer, when PSEL, PENABLE and PREADY are all high. At any other time it must be ignored. When high, it reports that the transfer failed, for example an access to an unmapped register or a write to a read-only one.

An error does not guarantee that nothing changed: for a write, the peripheral register may or may not have been updated, and for a read the returned data is not valid. It is up to the master, or the bridge in front of APB, to pass the error back to the requester.

Read more on APB Wait States and Errors.

What are the four HTRANS types in AHB?

• IDLE: no transfer is wanted. The slave must respond OKAY with zero wait states.
• BUSY: the master is in the middle of a burst but cannot continue this cycle. The slave ignores it and waits.
• NONSEQ: the first transfer of a burst, or a single transfer. The address is not related to the previous one.
• SEQ: a following transfer in a burst, whose address is the previous address plus the transfer size (or wrapped for WRAP bursts).

Read more on AHB Transfers and Pipelining.

How is AHB pipelined, and why must a slave check HREADY before sampling the address?

AHB overlaps the address phase of one transfer with the data phase of the previous one. While the data of transfer N is being moved, the address and control of transfer N+1 are already on the bus.

A slave may only sample a new address when HREADY is high, because HREADY low means the previous transfer's data phase is being extended, and the address on the bus is held, not yet accepted. A slave that samples whenever HSEL is high would see the same address several times during another slave's wait states and could, for example, perform a write twice.

Read more on AMBA AHB Protocol.

Name the five AXI channels.

• Write address (AW): address and control of a write.
• Write data (W): the write data beats, with WSTRB and WLAST.
• Write response (B): one response per write transaction.
• Read address (AR): address and control of a read.
• Read data (R): the read data beats, each with a response, and RLAST.

Each channel has its own VALID/READY handshake, so addresses, data and responses can move independently. There is no read response channel because each read data beat carries its own response.

Read more on AXI Channels and Handshake.

Can AXI write data arrive before the write address?

Yes. The write data channel is independent, so a master may send write data before, at the same time as, or after the address, and a slave must be able to accept it in any order. In practice many masters send address first, but a slave design must not assume that.

The write response on the B channel can only be sent after both the address and the last data beat (WLAST) have been accepted.

Read more on AXI Write Transactions.

What are AXI transaction IDs used for, and what ordering do they guarantee?

IDs let a master have many outstanding transactions and let the system return them out of order. Transactions with the same ID must complete in the order they were issued. Transactions with different IDs have no ordering relationship, so a fast slave can return its response before a slow slave that was addressed first.

Interconnects usually extend the ID with extra bits that identify the master, so that responses can be routed back. In AXI4, write data interleaving between different IDs was removed, so the W channel has no ID.

Read more on AXI Transaction IDs and Ordering.

What are the AXI burst types?

• FIXED: every beat uses the same address, used for FIFOs.
• INCR: the address increments by the transfer size each beat, used for normal memory.
• WRAP: the address increments but wraps at a boundary equal to the burst length times the transfer size, used for cache line fills that start at the critical word.

For example, a WRAP burst of 4 words (4 bytes each) starting at 0x34 has a 16-byte wrap boundary, so the addresses are 0x34, 0x38, 0x3C, 0x30. An AXI burst must also not cross a 4 KB address boundary.

Read more on AXI Burst Types.

What is the difference between SLVERR and DECERR?

SLVERR (slave error) means the transaction reached a slave, but the slave reported an error, for example an unsupported access size or a write to a read-only location. DECERR (decode error) means no slave exists at the address, and it is usually generated by the interconnect's default slave.

The difference helps software and debug: DECERR points to a wrong address or address map, SLVERR to a problem with the access itself.

Read more on AXI Responses and Exclusive Access.

What is AXI4-Lite, and when would you use it instead of full AXI4?

AXI4-Lite is a subset of AXI4 with the same five channels but no bursts (every transaction is one beat), no IDs, no exclusive accesses, and a data width of 32 or 64 bits. Every transaction is in order.

It is used for control and status registers, where bandwidth does not matter and a simple slave design is more important. Full AXI4 is used for memory and high-bandwidth data paths, and AXI4-Stream for data streams with no addresses.

Read more on AXI4-Lite.

What is a skid buffer, and why is it needed?

A skid buffer is a small two-entry buffer used to register a VALID/READY interface without losing data or bandwidth. If READY is simply registered, the upstream side only learns about back-pressure one cycle late and may send one more beat. The skid buffer catches that extra beat in a spare register.

It lets a pipeline stage break the combinational READY path for timing while still accepting one transfer per cycle.

Read more on AXI-Stream FIFO and Skid Buffer.

Describe a UART frame. How much baud rate mismatch can it tolerate?

An idle UART line is high. A frame starts with a start bit (low), then 5 to 9 data bits sent LSB first, an optional parity bit, and one or more stop bits (high). The receiver detects the falling edge of the start bit and samples each bit near its middle, usually with a 16x oversampling clock.

Because the receiver resynchronizes on every start bit, the error only accumulates within one frame. For a 10-bit frame, the sample point of the last bit must stay within about half a bit, which gives a total mismatch budget of roughly 5 %, usually shared between transmitter and receiver.

Read more on How UART Works.

What do CPOL and CPHA mean in SPI?

CPOL sets the idle level of the clock: 0 means SCLK idles low, 1 means it idles high. CPHA sets which edge samples the data: with CPHA 0, data is sampled on the first (leading) clock edge and changes on the second; with CPHA 1, data changes on the first edge and is sampled on the second.

The four combinations are SPI modes 0 to 3. Master and slave must use the same mode, otherwise data is sampled on the wrong edge and appears shifted by one bit.

Read more on How SPI Works.

Why are I2C lines open drain, and how do START, STOP and arbitration work?

SDA and SCL are open drain with pull-up resistors, so any device can pull a line low but none drives it high. This allows many devices on two wires without bus contention, lets a slave stretch the clock by holding SCL low, and makes arbitration possible.

START is SDA falling while SCL is high, and STOP is SDA rising while SCL is high. Normal data only changes while SCL is low. During arbitration, two masters transmit at once and each reads SDA back: a master that sends a 1 but sees a 0 has lost and stops, while the winner continues without its message being corrupted.

Read more on How I2C Works and I2C Arbitration.