Bus and interface questions come up in almost every design and verification interview, because every block in a chip talks to the rest through one. Interviewers rarely want the specification recited; they want to see that you understand why the rules exist and what goes wrong when they are broken. These questions cover the whole tutorial, from handshakes to I2C arbitration, with short answers and pointers to the article that explains each topic in depth.
15 min read | Intermediate
What You'll Learn
- Answer the most common AMBA questions: APB, AHB and AXI
- Explain the trade-offs between UART, SPI and I2C
- Reason about handshakes, deadlocks and ordering
- Approach bus design and verification questions
Fundamentals
1. What is the VALID/READY handshake and what is its one critical rule?
The sender raises VALID when it has data; the receiver raises READY when it can accept; the transfer happens at the clock edge where both are high. The critical rule: VALID must not wait for READY, and once raised it stays high with stable data until the transfer. Otherwise two components can each wait for the other forever. See Handshakes.
2. What is the difference between pipelining and outstanding transactions?
Pipelining overlaps the phases of consecutive transfers, as AHB overlaps the address of the next transfer with the data of the current one. Outstanding transactions let a master issue new requests before earlier ones complete, as AXI does, which hides the latency of slow slaves. See Pipelining and Outstanding Transactions.
3. Fixed priority or round robin arbitration?
Fixed priority is simple and gives guaranteed service to the top master, but can starve the others. Round robin is fair. Real systems often combine priority classes with round robin inside each class. See Arbitration.
APB
4. Why does every APB transfer take at least two cycles?
APB has a Setup phase (PSEL high, PENABLE low) and an Access phase (PENABLE high). The extra cycle gives the completer a full cycle to decode the address, which keeps peripherals simple and slow logic acceptable.
5. When is PSLVERR valid, and what does it mean for a write?
Only in the last cycle of the transfer, when PSEL, PENABLE and PREADY are all high. A write that receives PSLVERR may or may not have changed the register; that is peripheral-specific. See APB Wait States and Error Responses.
6. What did APB4 add?
PSTRB for byte writes and PPROT for protection (privileged, Non-secure, instruction). APB5 added optional wake-up, user signals, parity and RME.
AHB
7. What are the four HTRANS types?
IDLE (no transfer), BUSY (a pause inside a burst), NONSEQ (a single transfer or the first beat of a burst) and SEQ (the following beats). Slaves answer IDLE and BUSY with a zero-wait OKAY.
8. Why is an AHB ERROR response two cycles long?
Because of the pipeline: when the slave decides a transfer failed, the next address is already on the bus. The first cycle (HRESP high, HREADY low) gives the master time to cancel that next transfer; the second (HRESP high, HREADY high) completes the error. See AHB Wait States and Error Responses.
9. Why must a slave look at HREADY before sampling its address?
Another slave may be inserting wait states, which also holds the next address phase. A slave that samples whenever HSEL is high accepts transfers twice or accepts addresses still being held.
10. What is the address sequence of a WRAP4 burst of words starting at 0x34?
The wrap block is 4 x 4 = 16 bytes, 0x30 to 0x3F: 0x34, 0x38, 0x3C, 0x30.
Quick Check
Q: Why do AHB slave regions have a minimum size of 1 KB and AXI bursts a 4 KB boundary?
Show Answer
So that a burst can never cross from one slave into another. Masters must not start an incrementing burst that crosses the boundary, and slaves own whole aligned regions of at least that size.
AXI
11. Name the five AXI channels.
Write address (AW), write data (W), write response (B), read address (AR) and read data (R), each with its own VALID/READY.
12. Can write data arrive before its address?
Yes. AW and W are independent; data may come before, with or after the address. A slave may wait for one before accepting the other, but a master must never wait for AWREADY before asserting WVALID, or it can deadlock with a slave that waits for WVALID. See The Five AXI Channels and the VALID/READY Rules.
13. What are AXI IDs for, and what ordering do they guarantee?
Transactions with the same ID complete in order; different IDs may complete in any order. Reads and writes are never ordered against each other, even with the same ID. See AXI Transaction IDs and Ordering.
14. What changed from AXI3 to AXI4?
INCR bursts up to 256 beats, no write interleaving and no WID, no locked transactions (AxLOCK selects exclusive access only), new QoS, REGION and USER signals, and a write response that must follow the address.
15. How does an exclusive access work?
An exclusive read sets a monitor in the slave; an exclusive write to the same address with the same ID succeeds with EXOKAY only if nobody wrote the location in between. Otherwise it returns OKAY and does not update memory.
16. What is the difference between SLVERR and DECERR?
SLVERR comes from a real slave that received the access and failed it. DECERR comes from the interconnect's default slave when no slave owns the address.
17. Why does AXI4-Lite exist?
For register access: single-beat, full-width transactions without IDs, bursts or exclusive access, so register blocks stay small while still connecting to AXI interconnects.
18. What is a skid buffer?
A register slice that registers both the data path and READY at full throughput, by catching the one transfer that arrives in the cycle a stall is noticed in a second register. See Designing a Stream FIFO and Skid Buffer.
UART, SPI and I2C
19. Describe a UART frame.
Idle high, a start bit (low), 5 to 9 data bits LSB first (usually 8), an optional parity bit, and one or two stop bits (high).
20. How much baud rate mismatch can a UART tolerate?
The last sample comes about 9.5 bits after the start edge and must stay within half a bit, so roughly 5 percent in total between both sides, less in practice. See Designing a UART Receiver.
21. What do CPOL and CPHA mean in SPI?
CPOL is the idle level of SCLK. CPHA = 0 samples on the leading edge with the first bit set up before it; CPHA = 1 changes data on the leading edge and samples on the trailing edge. The four combinations are SPI modes 0 to 3.
22. Why are I2C lines open drain?
So that several devices can share them without fighting: any device can pull a line low, nobody drives it high. That makes ACK, clock stretching and multi-controller arbitration possible.
23. What are START and STOP in I2C?
START: SDA falls while SCL is high. STOP: SDA rises while SCL is high. Data only changes while SCL is low, so these two can never be confused with data.
24. Why does a register read use a repeated START?
The controller writes the register pointer, then needs to read, which requires a new address byte with R/W = 1. A repeated START changes direction without releasing the bus, so no other controller can step in and the target keeps its pointer.
25. How does I2C arbitration work?
Each controller checks SDA while sending. The first one to send a 1 but see a 0 has lost and stops driving; the winner's transfer is not disturbed. See I2C Multi-Master and Arbitration.
Quick Check
Q: A board needs to read one temperature sensor once a second and stream data from a 64 Mbit flash. Which interfaces?
Show Answer
I2C for the sensor (two pins, low rate, addressable) and SPI or quad SPI for the flash (bandwidth). See Choosing an Interface.
Design and Verification
26. How would you design an AXI4-Lite register slave?
Accept AW and W independently into holding registers, perform the write when both are present and the B channel is free, keep RDATA and BRESP stable while their VALID waits, use WSTRB for byte writes, and answer SLVERR for unmapped addresses.
27. What does a bridge from AHB to APB have to do?
Capture the AHB address phase, run the APB Setup and Access phases while holding HREADYOUT low, return PRDATA, and turn PSLVERR into a two-cycle AHB ERROR.
28. How do you verify a bus slave?
Random but legal stimulus, a reference model at the right granularity (bytes, for narrow and unaligned transfers), a scoreboard, protocol checks on every edge, and coverage of burst types, sizes, responses and corner cases.
29. What are typical protocol assertions for AXI?
VALID stays high and the payload stable until READY; WLAST and RLAST on the right beat; RID matches an outstanding ARID; BVALID only after the last write beat; no burst crosses 4 KB; WRAP lengths are 2, 4, 8 or 16.
30. Why should a bus monitor decode only the pins?
Because it must see what every other device sees. A monitor that uses internal signals of the driver or the DUT shares their view, and with it their bugs.
Running It in ChipVerify Lab
Every answer above has a runnable example in this tutorial. The AXI verification example is a good one to discuss in an interview: it combines stimulus, a model, a scoreboard and protocol checks, and finds a real bug.
Common Mistakes
Mistake #1: Reciting signals without the reason
"PENABLE is the second cycle" is a fact; "the extra cycle gives a slow peripheral time to decode" is understanding. Interviewers look for the second.
Mistake #2: Mixing protocol versions
RETRY and SPLIT belong to AMBA 2 AHB, WID to AXI3, locked transactions to AXI3. Say which version you mean.
Mistake #3: Forgetting ordering and deadlock
Many interview questions are really about who waits for whom. Check every answer against the handshake rules.
Practice Exercise
Challenge: Explain a Failure
An interviewer shows you this symptom: an AXI read burst of 4 beats returns correct data, but the master sees RLAST on beat 3. What checks would catch it, and what goes wrong afterwards? Then run the AXI verification example with the same bug planted, as its exercise describes.
Hint
What does the master think after an early RLAST, and what happens to the fourth beat?
Solution
A protocol check comparing the RLAST position with ARLEN fires on beat 3. After that, the master believes the burst ended and pairs the fourth beat with the next transaction, so a scoreboard sees a cascade of mismatches. The first protocol error points at the cause; the mismatches are only its effect. The AXI verification example shows exactly this.
Open the ready-made example in the lab and run the simulation.
Summary
- Handshakes, ordering and deadlock rules are the core of every bus question.
- APB: two-phase transfers; AHB: pipelined, two-cycle ERROR; AXI: five channels, IDs and outstanding transactions.
- UART, SPI and I2C trade pins, speed and topology; know their framing and timing rules.
- Bus design questions come down to accepting each channel correctly and keeping outputs stable.
- Verification answers combine stimulus, models, scoreboards, protocol checks and coverage.
