Designing an SPI Master

An SPI master generates the clock, shifts a byte out on MOSI while shifting a byte in from MISO, and controls chip select. Supporting all four SPI modes takes only a few lines more than supporting one, if the design is built around leading and trailing edges instead of rising and falling ones. This article builds such a master and looks at what limits its clock speed.

8 min read | Intermediate

What You'll Learn

• Generate SCLK from a system clock with a divider
• Shift data out and in on the correct edges for any mode
• Control chip select across multi-byte transactions
• Understand the timing margins between master and slave

The Plan

• A divider counts CLK_DIV system clocks for every half period of SCLK. Each time it expires, SCLK toggles: that is one edge.
• A byte takes 16 edges. Even-numbered edges (0, 2, ...) are leading edges and odd-numbered edges are trailing edges, whatever CPOL is.
• For CPHA = 0: put the first bit on MOSI at the start, sample MISO on leading edges, change MOSI on trailing edges. For CPHA = 1: change MOSI on leading edges, sample on trailing edges.
• Chip select is controlled separately with cs_req, so that several bytes can be sent in one transaction.

The RTL

// SPI master: one byte per transfer, MSB first, any of the four modes.
//   CLK_DIV  system clocks per half SCLK period
//   CPOL     SCLK level when idle
//   CPHA     0: sample on the leading edge, change on the trailing edge
//            1: change on the leading edge, sample on the trailing edge
// cs_req holds the chip select active across several bytes.
module spi_master #(
  parameter CLK_DIV = 4,
  parameter CPOL    = 0,
  parameter CPHA    = 0
) (
  input            clk,
  input            rst,
  input            start,              // begin a byte transfer (when not busy)
  input      [7:0] tx_byte,
  input            cs_req,             // 1: keep chip select active
  output reg       busy,
  output reg       done,               // one-cycle pulse: rx_byte is valid
  output reg [7:0] rx_byte,
  output reg       sclk,
  output reg       mosi,
  input            miso,
  output           cs_n
);
  reg [15:0] div;
  reg [4:0]  edges;                    // SCLK edges so far in this byte (16 per byte)
  reg [7:0]  tx_sh;
  reg [7:0]  rx_sh;

  assign cs_n = !cs_req;

  always @(posedge clk) begin
    if (rst) begin
      busy <= 1'b0;
      done <= 1'b0;
      sclk <= CPOL;
      mosi <= 1'b0;
    end
    else begin
      done <= 1'b0;
      if (!busy) begin
        sclk <= CPOL;
        if (start) begin
          busy  <= 1'b1;
          div   <= 16'd0;
          edges <= 5'd0;
          tx_sh <= tx_byte;
          if (CPHA == 0)
            mosi <= tx_byte[7];        // the first bit must be ready before the first edge
        end
      end
      else if (div == CLK_DIV - 1) begin
        div <= 16'd0;
        if (edges == 5'd16) begin      // all 16 edges done
          busy    <= 1'b0;
          done    <= 1'b1;
          rx_byte <= rx_sh;
        end
        else begin
          sclk  <= ~sclk;
          edges <= edges + 5'd1;
          if (edges[0] == 1'b0) begin  // leading edge
            if (CPHA == 0) begin
              rx_sh <= {rx_sh[6:0], miso};             // sample
            end
            else begin
              mosi  <= tx_sh[7];                       // change
              tx_sh <= {tx_sh[6:0], 1'b0};
            end
          end
          else begin                   // trailing edge
            if (CPHA == 0) begin
              mosi  <= tx_sh[6];                       // change: the next bit
              tx_sh <= {tx_sh[6:0], 1'b0};
            end
            else begin
              rx_sh <= {rx_sh[6:0], miso};             // sample
            end
          end
        end
      end
      else begin
        div <= div + 16'd1;
      end
    end
  end
endmodule

SCLK idles at CPOL while the master is not busy. Shift registers shift left because SPI sends the most significant bit first. done pulses half a clock after the sixteenth edge, when rx_byte holds the byte that came in.

Driving It

The testbench wraps the byte interface in a task and holds chip select over a two-byte transaction:

task xfer(input [7:0] b, output [7:0] got);
  begin
    @(posedge clk);
    tx_byte <= b;
    start   <= 1;
    @(posedge clk);
    start   <= 0;
    @(posedge done);
    got = rx_byte;
  end
endtask

task access(input rw, input [1:0] addr, input [7:0] wdata);
  reg [7:0] id;
  reg [7:0] rdata;
  begin
    cs_req <= 1;
    repeat (4) @(posedge clk);
    xfer({rw, 5'b0, addr}, id);
    xfer(rw ? wdata : 8'h00, rdata);
    repeat (2) @(posedge clk);
    cs_req <= 0;
    // ...
  end
endtask

SPI mode 0 (CPOL=0, CPHA=0)
1535  write reg1 = 0x3c   (slave ID 0xa5)
3055  write reg2 = 0xc3   (slave ID 0xa5)
4575  read  reg1 = 0x3c   (slave ID 0xa5)
6095  read  reg2 = 0xc3   (slave ID 0xa5)

The few clock cycles between chip select and the first edge, and after the last edge, give the slave setup and hold time on CS_n. Real devices specify these in their datasheets, often a few nanoseconds to tens of nanoseconds.

What Limits the Clock

The master samples MISO half an SCLK period after the slave changed it. In that half period the slave's output must change, travel across the board and arrive at the master in time. On a PCB with a fast slave that allows tens of MHz. Inside a chip, a slave that oversamples SCLK with its own clock adds a synchronizer delay of two or three of its clock cycles, which must fit in the half period too.

Running It in ChipVerify Lab

The example contains this master and the register slave. Change CLK_DIV and the mode, and watch the timing between SCLK edges and MISO changes.

Common Mistakes

SPI mode 0 (CPOL=0, CPHA=0)
855  write reg1 = 0x3c   (slave ID 0xd2)
1695  write reg2 = 0xc3   (slave ID 0xd2)
2535  read  reg1 = 0x1e   (slave ID 0xd2)
3375  read  reg2 = 0xe1   (slave ID 0xd2)