APB moves one register value every two cycles, which is plenty for a UART and far too slow for memory. AHB is the next step up: a pipelined bus that starts a new transfer every cycle, supports bursts, and still keeps the rules simple enough for a small microcontroller. This chapter covers how AHB works and then designs and verifies an AHB-Lite memory slave.
The AHB protocol (Advanced High-performance Bus) is the AMBA bus for memories, memory controllers and other blocks that need more bandwidth than APB but not the complexity of AXI. Its key idea is pipelining: every transfer has an address phase and a data phase, and the address phase of the next transfer overlaps the data phase of the current one. This article introduces the parts of an AHB system and the signals between them.
8 min read | Intermediate
What You'll Learn
- Describe what AHB is used for and how it differs from APB
- Name the parts of an AHB-Lite system: master, slaves, decoder and multiplexor
- List the AHB signals and say which phase each belongs to
- Tell AHB-Lite, AHB5 and the original AMBA 2 AHB apart
Where AHB Is Used
The specification names the typical AHB slaves: internal memories, external memory interfaces and high-bandwidth peripherals. Low-bandwidth peripherals usually sit on APB behind an APB bridge, which is itself an AHB slave. In a microcontroller, the processor, its flash and SRAM, and a DMA engine often share an AHB bus, while timers and serial ports live on APB.
Compared with APB, AHB adds three things:
- Pipelining: a new transfer can start in every cycle.
- Bursts: a master can announce a sequence of 4, 8 or 16 related transfers, or one of undefined length.
- Wider data: 32 bits is the recommended minimum, and the data buses can be up to 1024 bits wide.
Like APB, AHB uses one clock edge (the rising edge of HCLK) and no tristate buses, so read data and write data travel on separate buses.
Versions: AMBA 2 AHB, AHB-Lite and AHB5
The name AHB covers three versions, and old articles and IP often mix them up:
- AMBA 2 AHB (1999) supported several masters on one bus, with request and grant signals to an arbiter, and slaves could answer with RETRY or SPLIT to free the bus.
- AHB-Lite (AMBA 3) has a single master. It dropped arbitration, RETRY and SPLIT, and
HRESPbecame one bit: OKAY or ERROR. Systems with several masters use an interconnect that gives each master its own AHB-Lite port. - AHB5 (AMBA 5) is AHB-Lite plus optional extensions, each enabled by a property: secure transfers, extended memory types, exclusive transfers and user signals, among others.
This chapter describes AHB-Lite, which is what you will meet in almost every current design. The AHB5 specification calls both AHB-Lite and AHB5 simply "AHB".
The Parts of an AHB-Lite System
- Master: starts every transfer by driving the address and control signals, and the write data for writes.
- Slaves: answer the transfers addressed to them. Each slave reports when a transfer is finished and whether it succeeded.
- Decoder: looks at the high address bits and raises one select signal,
HSELx, for the slave that owns the address. - Multiplexor: passes the read data and response from the selected slave back to the master.
The address, control and write data go to every slave at once; only the selected slave acts on them. Every system with two or more slaves needs one central decoder and one central multiplexor. A system whose memory map has gaps also needs a default slave that answers accesses to the gaps, covered in AHB with Multiple Slaves.
Quick Check
Q: An AHB-Lite system has a processor and a DMA engine that both need the bus. Can they share one AHB-Lite bus directly?
Show Answer
No. AHB-Lite has a single master and no arbitration signals. The two masters each get their own AHB-Lite port into an interconnect, which arbitrates between them.
The AHB-Lite Signals
All signals start with H. Most of the master's signals belong to the address phase; only the write data belongs to the data phase.
| Signal | Driven by | Phase | Meaning |
|---|---|---|---|
| HCLK | Clock source | - | Bus clock; all timing is on its rising edge |
| HRESETn | Reset controller | - | Reset, active low (the only active-low AHB signal) |
| HADDR[31:0] | Master | Address | Byte address |
| HTRANS[1:0] | Master | Address | Transfer type: IDLE, BUSY, NONSEQ or SEQ |
| HWRITE | Master | Address | 1 = write, 0 = read; constant through a burst |
| HSIZE[2:0] | Master | Address | Transfer size: byte, halfword, word or wider |
| HBURST[2:0] | Master | Address | Burst type: SINGLE, INCR, WRAP4, INCR4 ... |
| HPROT[3:0] | Master | Address | Protection: data or opcode, privileged, bufferable, modifiable |
| HMASTLOCK | Master | Address | The transfer is part of a locked sequence |
| HWDATA | Master | Data | Write data |
| HSELx | Decoder | Address | Selects one slave |
| HRDATA | Slave, via multiplexor | Data | Read data |
| HREADYOUT | Slave | Data | High when the slave finishes its transfer; low inserts a wait state |
| HRESP | Slave, via multiplexor | Data | 0 = OKAY, 1 = ERROR |
| HREADY | Multiplexor | Data | The selected slave's HREADYOUT, sent to the master and all slaves |
HREADY and HREADYOUT
These two names cause the most confusion. Each slave drives its own HREADYOUT. The multiplexor picks the one from the slave that owns the current data phase and sends it out as HREADY. That single HREADY goes to the master and back into every slave.
Why does a slave need HREADY as an input? Because the address phase of the next transfer can be stretched by a wait state from a different slave. A slave must only accept a new transfer when HSEL is high and HREADY is high, which means the previous transfer on the bus has completed. A slave that ignores HREADY can accept the same transfer twice, or one that never really happened.
Quick Check
Q: Slave A is selected for the next transfer while slave B is still inserting wait states. Which HREADY value does slave A see, and what should it do?
Show Answer
It sees HREADY low, because the multiplexor is passing slave B's HREADYOUT. Slave A must wait: it accepts its transfer only at the edge where HREADY is high.
Running It in ChipVerify Lab
The example for this chapter is an AHB-Lite memory slave with a small master that runs a list of transfers. Open it to see every signal from the table above in one waveform.
Common Mistakes
Mistake #1: Treating AHB-Lite as multi-master
HBUSREQ, HGRANT, RETRY and SPLIT belong to AMBA 2 AHB. An AHB-Lite slave has none of them, and a two-bit HRESP is a sign of AMBA 2 IP.
Mistake #2: Connecting HREADYOUT straight to the master
With more than one slave, the master must get the HREADYOUT of the slave in the data phase, through the multiplexor. Feeding it from one slave, or from an OR of all slaves, breaks wait states.
Mistake #3: A slave that ignores HREADY
A slave must sample HSEL, the address and the control signals only when HREADY is high. Otherwise it reacts to address phases that are still being held.
Practice Exercise
Challenge: Read the Waveform
Open the example and run it. For the first write, find the cycle where its address is on HADDR and the cycle where its data is on HWDATA. Which signals change in each of the two cycles?
Hint
Look for HTRANS = NONSEQ: that cycle is the address phase. The data phase is the next cycle in which HREADY is high.
Solution
In the address phase, HADDR = 0x10, HTRANS = NONSEQ, HWRITE = 1, HSIZE = WORD and HBURST = SINGLE. In the next cycle (the data phase), HWDATA carries 0xA1 while HTRANS has already moved on to IDLE. The write completes at the end of that cycle because HREADY is high.
Open the ready-made example in the lab and run the simulation.
Summary
- AHB is the AMBA bus for memories and high-bandwidth slaves; peripherals sit on APB behind a bridge.
- An AHB-Lite system has one master, one decoder, one multiplexor and any number of slaves.
- Address and control signals belong to the address phase; write data, read data and the response belong to the data phase.
- Each slave drives
HREADYOUT; the selected one becomesHREADYfor the master and all slaves. - AHB-Lite is single-master with an OKAY/ERROR response; AMBA 2 AHB added arbitration, RETRY and SPLIT, and AHB5 adds optional extensions.