Full AXI4 is built for moving bursts of data between processors and memories. Most blocks in a chip do something simpler: they have a few control and status registers that software reads and writes one word at a time. This chapter covers the two lighter members of the AXI4 family: AXI4-Lite for register access, and AXI4-Stream for data that flows without addresses.
AXI4-Lite is the subset of AXI4 for simple, register-style interfaces. It keeps the five channels and the VALID/READY handshake, so it connects to an AXI interconnect without a protocol change, but every transaction is a single beat that uses the full data bus. There are no bursts, no transaction IDs and no exclusive accesses. This article lists exactly what AXI4-Lite keeps and drops, and what that means for masters, slaves and the interconnect between them.
7 min read | Intermediate
What You'll Learn
- List the signals of an AXI4-Lite interface
- Explain what AXI4-Lite gives up compared with AXI4
- Use write strobes for byte-wide register writes
- Connect AXI4-Lite slaves to full AXI4 masters
The Rules of AXI4-Lite
The specification defines AXI4-Lite in a few lines:
- every transaction has a burst length of 1;
- every access uses the full width of the data bus, which is 32 or 64 bits;
- every access is Non-modifiable and Non-bufferable;
- exclusive accesses are not supported, so EXOKAY never appears.
Those rules remove most of the AXI4 signals:
What remains is: AWADDR, AWPROT, WDATA, WSTRB, BRESP, ARADDR, ARPROT, RDATA, RRESP, plus VALID and READY on each channel and the global ACLK and ARESETn. Without bursts there is nothing for AxLEN, AxSIZE, AxBURST, WLAST or RLAST to describe; every beat is the last one.
Quick Check
Q: Can an AXI4-Lite master have several transactions in flight?
Show Answer
Yes. AXI4-Lite supports multiple outstanding transactions, but a slave may restrict this with its READY signals. Because there are no IDs, all responses come back in order.
Write Strobes Still Matter
AXI4-Lite keeps WSTRB. Masters and interconnects must always drive correct strobes, which lets software write a single byte of a register. A slave has three choices:
- use the strobes fully;
- ignore them and treat every write as a full-width write;
- detect strobe combinations it does not support and answer with an error.
A slave that provides memory must support the strobes fully. A register block may choose a simpler option, as long as its documentation says so.
Responses
BRESP and RRESP can be OKAY, SLVERR or DECERR, but never EXOKAY. A register block typically answers SLVERR for an address it does not implement, and the interconnect's default slave answers DECERR for an address that belongs to no slave.
A Register Slave in Action
The register slave from Designing an AXI4-Lite Register Slave has a read/write CTRL register, a byte-writable DATA register, a read-only COUNT of accepted writes and a read-only ID. The full AXI4 testbench master drives it with single-beat transactions:
35 AW id=0 addr=0x000 len=0 size=4 INCR 35 W data=0x000000c1 strb=1111 last 55 W data=0x11223344 strb=1111 last 55 B id=0 OKAY 75 AW id=0 addr=0x004 len=0 size=4 INCR 95 AW id=0 addr=0x004 len=0 size=4 INCR 95 B id=0 OKAY 145 W data=0xaa000000 strb=1000 last 165 AW id=0 addr=0x00c len=0 size=4 INCR 165 W data=0xffffffff strb=1111 last 165 B id=0 OKAY 185 AW id=0 addr=0x040 len=0 size=4 INCR 185 W data=0x12345678 strb=1111 last 185 B id=0 OKAY 205 B id=0 SLVERR 215 AR id=0 addr=0x000 len=0 size=4 INCR 225 R id=0 data=0x000000c1 OKAY last 235 AR id=0 addr=0x004 len=0 size=4 INCR 245 R id=0 data=0xaa223344 OKAY last 255 AR id=0 addr=0x008 len=0 size=4 INCR 265 R id=0 data=0x00000004 OKAY last 275 AR id=0 addr=0x00c len=0 size=4 INCR 285 R id=0 data=0x41584c31 OKAY last 295 AR id=0 addr=0x040 len=0 size=4 INCR 305 R id=0 data=0x00000000 SLVERR last
The single-byte write with WSTRB = 1000 changed only the top byte of DATA, which reads back as 0xAA223344. The write to the read-only ID register was ignored (ID still reads 0x41584C31), and the accesses to 0x040, where there is no register, got SLVERR. Every R beat has RLAST high, because in AXI4-Lite every transfer is the last.
AXI4 Masters and AXI4-Lite Slaves
Three of the four combinations just work: an AXI4-Lite master on an AXI4 slave, and Lite on Lite, and full on full. The case that needs care is a full AXI4 master talking to an AXI4-Lite slave:
- ID reflection: the master expects its ID back on
BIDandRID. Either a bridge stores and returns the ID, or the Lite slave includes ID reflection logic itself. - Conversion: if the master might send bursts, a converter splits each burst into single transactions, combines their write responses into one (any error wins), and drops
AxLOCKandAxCACHE. An exclusive write through such a converter always fails.
In practice, AXI interconnects include these converters on their Lite ports, so a register block can stay simple.
Quick Check
Q: An AXI4 master sends a four-beat write burst to an AXI4-Lite slave through a converter, and the third beat fails. What response does the master get?
Show Answer
The converter turns the burst into four single writes and combines their four responses into one. Errors are sticky, so the master receives one write response with the error.
Running It in ChipVerify Lab
The example contains the register slave and the testbench above. Change the strobes of the byte write and predict the DATA value before you run it.
Common Mistakes
Mistake #1: Sending a burst to an AXI4-Lite slave
A Lite slave ignores AxLEN. A burst sent straight to it is treated as one beat and the remaining data upsets the following transactions. Put a converter in between if the master can issue bursts.
Mistake #2: Forgetting the IDs
Connected directly to a full AXI master, a Lite slave must reflect AWID and ARID on BID and RID, or the master cannot match its responses.
Mistake #3: Choosing a 16-bit or 128-bit AXI4-Lite bus
AXI4-Lite allows only 32-bit and 64-bit data buses. Use 64 bits only for registers that need 64-bit atomic access.
Practice Exercise
Challenge: Two Middle Bytes
Change the strobes of the third write from 1000 to 0110, keeping the data 0xAA000000. What does DATA read back as?
Hint
Strobe bits 1 and 2 enable bytes 1 and 2 of WDATA. What does 0xAA000000 carry in those bytes?
Solution
245 R id=0 data=0x11000044 OKAY last
Bytes 1 and 2 of 0xAA000000 are both 0x00, so they replace 0x33 and 0x22 in 0x11223344. Bytes 0 and 3 keep their values: 0x11000044. The 0xAA in byte 3 is ignored because its strobe is low.
Open the ready-made example in the lab and run the simulation.
Summary
- AXI4-Lite is AXI4 with single-beat, full-width transactions: no bursts, no IDs, no exclusive access.
- It keeps the five channels, VALID/READY, the addresses,
AxPROT,WSTRBand the responses. - The data bus is 32 or 64 bits; every R transfer counts as the last.
- Slaves may use, ignore or reject write strobes; memories must use them.
- A full AXI4 master needs ID reflection and burst conversion to talk to a Lite slave.
