Most on-chip buses in use today belong to one family: Arm's AMBA. Its protocols are free to use, and processors, memory controllers and peripheral IP from many vendors speak them, so a chip can be assembled from parts that plug together. This chapter starts with APB, the smallest member of the family, and builds and verifies real APB peripherals along the way.
AMBA (Advanced Microcontroller Bus Architecture) is a set of on-chip bus protocols. APB, AHB and AXI are the three you will meet most often. They differ in how much they do: APB moves one register value at a time, AHB adds pipelining and bursts, and AXI splits a transfer into independent channels so many transactions can be in flight. This article gives you a map of the family before the details.
7 min read | Beginner to Intermediate
What You'll Learn
- Name the AMBA protocols and the generation each one came from
- Compare APB, AHB and AXI on pipelining, bursts and outstanding transactions
- Pick the right protocol for a given block in a chip
- Read the naming used in the specifications
Four Generations
AMBA has grown over four generations. Each one kept the older protocols and added new ones, so a modern chip often uses protocols from several generations side by side.
- AMBA 2 (1999) defined AHB and APB, plus ASB, an older system bus that AHB replaced.
- AMBA 3 introduced AXI (now called AXI3), AHB-Lite, a single-master version of AHB, and APB3, which added wait states and error responses to APB.
- AMBA 4 brought AXI4, its register-access subset AXI4-Lite, AXI4-Stream for data that has no address, ACE for cache coherency, and APB4 with write strobes and protection.
- AMBA 5 added AHB5, APB5, AXI5 and CHI, a packet-based protocol for large coherent systems.
Version numbers matter when you connect IP. An APB3 completer has no PSTRB input, for example, so an APB4 requester that drives it needs a small adapter or a rule that it only writes whole words.
APB, AHB and AXI Side by Side
The three protocols use the same basic ideas you have already seen: address decoding, handshakes, wait states and errors. They differ in how far they go with pipelining and concurrency.
| APB | AHB | AXI | |
|---|---|---|---|
| Typical use | Peripheral registers | Simple system bus, microcontrollers | High-performance system bus |
| Cycles per transfer | At least 2 | 1 when pipelined | 1 per beat on each channel |
| Pipelining | None | Address of the next transfer overlaps data of the current one | Independent address, data and response channels |
| Bursts | No | Yes: 4, 8 or 16 beats, or undefined length | Yes, up to 256 beats (AXI4 incrementing) |
| Outstanding transactions | One | One data phase at a time | Many, with IDs for reordering |
| Handshake | PREADY | HREADY | VALID/READY on every channel |
| Gate count | Smallest | Medium | Largest |
The pattern is a trade between performance and size. APB is cheap enough to put in front of every UART and timer. AXI costs more logic but keeps a memory controller busy with many reads in flight. AHB sits in between and is still common in microcontrollers.
Quick Check
Q: Which of the three protocols can have several read transactions waiting for data at the same time?
Show Answer
AXI. Its read address channel can accept new requests while earlier ones are still waiting for data, and transaction IDs tell the master which response belongs to which request. APB and AHB allow one transaction at a time.
How They Fit Together in a Chip
A typical system uses all three. Processors, DMA engines and the memory controller sit on an AXI interconnect, where bandwidth matters. Slower masters and on-chip memories may sit on AHB. Peripherals such as UARTs, timers, GPIO and I2C controllers sit on APB behind a bridge. The bridge is the only requester on its APB bus: it turns an AXI or AHB transfer into an APB transfer and passes the result back.
This layering keeps the fast part of the chip small. A processor that writes to a timer register crosses the AXI interconnect and the bridge, then spends two or three APB cycles on the timer. The AXI side meanwhile keeps serving other masters.
Names in the Specifications
Each protocol prefixes its signals with one letter: P for APB (PADDR, PSEL), H for AHB (HADDR, HTRANS), and channel names for AXI (AWADDR, RDATA). Active-low signals end in n, as in PRESETn.
The words for the two ends have changed over the years. Older specifications say master and slave. The current APB specification says Requester and Completer, and newer AXI and AHB issues use Manager and Subordinate. They mean the same thing: the side that starts a transfer and the side that answers it. This tutorial uses requester and completer in the APB articles and master and slave elsewhere, to match the specification you will be reading next to it.
What This Chapter Covers
The full specifications are free from Arm and are the right place for every detail. These articles focus on how each protocol works, why its rules exist, and how to design and verify blocks that use it. For APB you will:
- Follow the Setup and Access phases of a transfer in APB Bus Protocol
- Add slow registers and errors in APB Wait States and Error Responses
- Use byte strobes and protection in APB4 and APB5
- Build a timer peripheral in Designing an APB Register Block
- Check it with a self-checking testbench in Verifying an APB Slave
Quick Check
Q: A new block has eight control registers that the processor writes once at boot. Which protocol would you give it?
Show Answer
APB. The registers are accessed rarely and one at a time, so AHB or AXI would only add logic. The block sits behind the APB bridge with the other peripherals.
Common Mistakes
Mistake #1: Putting every block on AXI
An AXI interface on a block with four registers costs far more logic and verification effort than it saves. Give low-bandwidth register blocks an APB interface.
Mistake #2: Assuming every APB block has the same signals
APB2 has no PREADY or PSLVERR, APB3 has no PSTRB or PPROT. Check which version each block implements before you connect it.
Mistake #3: Expecting bursts on APB
APB transfers one value at a time. Software that copies a buffer to an APB peripheral makes one transfer per word, which is fine for a peripheral and the reason large data never goes over APB.
Practice Exercise
Challenge: Place the Blocks
A chip contains a processor, a DDR memory controller, a DMA engine, a 64 KB on-chip SRAM, two UARTs, a timer and a GPIO block. Decide which bus each block connects to and where the bridges go. Then open the APB register example from the next article and look at how few signals a completer needs.
Hint
Ask which blocks move large amounts of data and which only have registers.
Solution
The processor, DMA engine and DDR controller go on AXI, since they need bandwidth and several transactions in flight. The SRAM can go on AXI or on AHB behind an AXI-to-AHB bridge. The UARTs, timer and GPIO go on APB behind an AXI-to-APB bridge (or AHB-to-APB). The bridge is the only requester on the APB bus.
Open the ready-made example in the lab and run the simulation.
Summary
- AMBA is a family of on-chip bus protocols; APB, AHB and AXI are the most common.
- APB is for peripheral registers, AHB is a simple pipelined system bus, and AXI is the high-performance bus with independent channels.
- Each generation added protocols and features: APB3 added wait states and errors, APB4 added strobes and protection.
- A chip uses all three, with bridges between them; the APB bridge is the only requester on its bus.
- Requester and completer, master and slave, manager and subordinate all name the same two roles.