Bridges: AHB to APB and AXI to APB

A bridge connects two buses that speak different protocols. The most common AMBA bridges go from AXI or AHB down to APB, so that the processor can reach the peripheral registers. On one side the bridge is a slave; on the other it is the only requester. This article builds an AHB-to-APB bridge, follows transfers through it in a simulation, and explains how an AXI-to-APB bridge differs.

8 min read | Intermediate

What You'll Learn

• Explain what a bridge does on each of its two sides
• Design an AHB-to-APB bridge as a small state machine
• Map APB wait states and PSLVERR onto AHB and AXI responses
• Estimate the cost of reaching a peripheral through a bridge

Two Sides, Two Roles

On the AHB side the bridge is an ordinary AHB slave: it is selected by the decoder, captures the address phase, and controls the data phase with HREADYOUT. On the APB side it is the APB requester, the only one on that bus, which drives PSEL, PENABLE, PADDR, PWRITE and PWDATA. The bridge's job is to turn one AHB transfer into one APB transfer and hold the AHB side until the APB side is finished.

The State Machine

Three states follow the APB protocol, plus one for the second cycle of an AHB ERROR:

localparam IDLE = 2'd0, SETUP = 2'd1, ACCESS = 2'd2, ERR2 = 2'd3;

wire start = HREADY && HSEL && HTRANS[1];        // an AHB transfer for the bridge
wire done  = (state == ACCESS) && PREADY;         // the APB transfer completes

always @(posedge HCLK) begin
  if (!HRESETn) begin
    state <= IDLE;
  end
  else begin
    case (state)
      SETUP:
        state <= ACCESS;
      ACCESS:
        if (PREADY)
          state <= PSLVERR ? ERR2 : (start ? SETUP : IDLE);
      default:                                    // IDLE and ERR2
        state <= start ? SETUP : IDLE;
    endcase
    if (start) begin
      PADDR  <= HADDR[11:0];                      // capture the address phase
      PWRITE <= HWRITE;
    end
  end
end

// APB side: Setup and Access phases
assign PSEL    = (state == SETUP) || (state == ACCESS);
assign PENABLE = (state == ACCESS);
assign PWDATA  = HWDATA;                          // the AHB master holds HWDATA while we wait

// AHB side: wait until the APB transfer is done; PSLVERR gives a two-cycle ERROR
assign HREADYOUT = (state == IDLE) || (state == ERR2) || (done && !PSLVERR);
assign HRESP     = (done && PSLVERR) || (state == ERR2);
assign HRDATA    = PRDATA;

The bridge captures the AHB address at the end of the address phase and starts the APB Setup phase in the next cycle, which is the AHB data phase. Write data needs no register: the AHB master must hold HWDATA for as long as HREADYOUT is low, so it stays stable through the whole APB transfer. When PREADY arrives, the AHB transfer completes in the same cycle, and the next AHB address, held during the wait, is captured at once.

Errors Across the Bridge

APB reports an error with PSLVERR in the last cycle of the transfer. AHB needs a two-cycle ERROR: HRESP high with HREADYOUT low, then HRESP high with HREADYOUT high. The bridge uses the cycle in which PSLVERR arrives as the first ERROR cycle and adds state ERR2 for the second. The APB specification describes these mappings: an AHB-to-APB bridge maps PSLVERR to HRESP, and an AXI-to-APB bridge maps it to RRESP for reads and BRESP for writes.

The Simulation

The AHB master from the AHB chapter talks through the bridge to the APB completer from APB Wait States and Error Responses, which has a fast CTRL register, a buffer with two wait states, a read-only ID and unmapped addresses:

burst(1, SINGLE, 32'h000, WORD, 1, 32'h3);           // CTRL: no APB wait states
burst(1, SINGLE, 32'h014, WORD, 1, 32'hBEEF0014);    // BUF[1]: two APB wait states
burst(0, SINGLE, 32'h014, WORD, 1, 0);
burst(0, SINGLE, 32'h020, WORD, 1, 0);               // ID register
burst(1, SINGLE, 32'h020, WORD, 1, 32'hFFFFFFFF);    // read-only: PSLVERR
burst(0, SINGLE, 32'h000, WORD, 1, 0);

45  write 0x0000 = 0x00000003  OKAY
85  write 0x0014 = 0xbeef0014  OKAY
125  read  0x0014 = 0xbeef0014  OKAY
145  read  0x0020 = 0x0a9b0001  OKAY
175  write 0x0020 = 0xffffffff  ERROR
195  read  0x0000 = 0x00000003  OKAY

Every AHB transfer now costs at least two cycles of data phase, one for APB Setup and one for Access, plus the APB wait states. The buffer accesses take four. The write to the read-only ID gets PSLVERR, and the master sees a normal two-cycle AHB ERROR.

AXI to APB

An AXI-to-APB bridge has the same APB side. On the AXI side it is an AXI slave with five channels:

• a write needs both the AW address and the W data before the APB write can start, and its response goes back on B;
• a read starts the APB read from the AR address and returns the data on R;
• APB handles one transfer at a time, so the bridge serializes AXI reads and writes, and usually splits bursts into single APB transfers;
• the bridge must return the AXI ID on BID and RID, and PSLVERR becomes SLVERR.

Because APB is slow and simple, bridges are often placed behind a register slice or on a slower clock. Many SoCs run the APB bus at half or a quarter of the AXI clock, which makes the bridge a clock domain crossing as well.

Running It in ChipVerify Lab

The example contains the bridge, the APB completer and the AHB master. Compare the AHB and APB signals in the waveform.

Common Mistakes

assign PREADY = hit_buf ? (wcnt == 2'd3) : 1'b1;

45  write 0x0000 = 0x00000003  OKAY
95  write 0x0014 = 0xbeef0014  OKAY
145  read  0x0014 = 0xbeef0014  OKAY
165  read  0x0020 = 0x0a9b0001  OKAY
195  write 0x0020 = 0xffffffff  ERROR
215  read  0x0000 = 0x00000003  OKAY