A plain UART frame has no protection: a bit flipped by noise just becomes a wrong byte. Three additions make UART links more robust. A parity bit detects single-bit errors, RTS/CTS flow control stops a sender from overrunning a busy receiver, and physical layers such as RS-232 and RS-485 carry the signal further than a logic-level wire. This article shows parity and flow control in a simulation and explains the physical layers.
8 min read | Intermediate
What You'll Learn
- Generate and check even and odd parity
- Explain what parity can and cannot detect
- Use RTS/CTS hardware flow control
- Compare logic-level UART, RS-232 and RS-485
Parity
The parity bit goes between the last data bit and the stop bit. With even parity, the transmitter sets it so that the data bits plus the parity bit contain an even number of ones; with odd parity, an odd number. The receiver recomputes the parity of what it received and compares. Settings are written like "8E1": 8 data bits, even parity, 1 stop bit, 11 bit times per frame.
In hardware, parity is a running XOR. The transmitter and the receiver both start from 0 for even parity (1 for odd) and XOR in every data bit:
par <= par ^ shreg[0]; // transmitter, once per data bit
// ...
tx <= par; // the parity bit
par <= par ^ rx_s2; // receiver, once per data bit
// ...
parity_err <= (par != rx_s2); // compare with the received parity bit
Parity in Action
The testbench uses even parity and flips the line for 40 ns in the middle of data bit 3 of the byte 0x55, as a noise spike would:
25 tx sends 0x4b 1755 rx got 0x4b 1795 tx sends 0x55 3525 rx got 0x5d PARITY ERROR 3565 tx sends 0xa3 5295 rx got 0xa3 6565 tx sends 0x0f 8295 rx got 0x0f
Bit 3 of 0x55 was 0 and was received as 1, giving 0x5D. The number of ones no longer matches the parity bit, so the receiver flags the byte. What to do with it is up to the software: discard it, ask for a retransmission, or count errors to judge the link quality.
Quick Check
Q: Can parity tell which bit was wrong?
Show Answer
No. A single parity bit only says that an odd number of bits changed. It cannot locate the error, and it cannot correct it.
Flow Control with RTS and CTS
A receiver that cannot keep up, for example because its FIFO is full and software is busy, needs a way to pause the sender. Hardware flow control adds two wires: each side drives RTS (request to send, really "I can receive") and reads CTS from the other side. Both are active low. When the receiver's buffer nears full, it deasserts its RTS; the sender sees CTS deasserted and stops after the current frame.
In the simulation, cts_n goes high while 0xA3 is being sent. That frame completes normally, then the transmitter keeps ready low until cts_n falls at 6565 ns, and 0x0F goes out. The receiver should deassert RTS while it still has room for a few more bytes, because the sender may be in the middle of a frame when it notices.
Software flow control does the same in-band, with the XOFF (0x13) and XON (0x11) characters, which saves the two wires but cannot be used for binary data that might contain those values.
Physical Layers
- Logic level (often called TTL): the UART pins of a chip, 3.3 V or 1.8 V, idle high. Fine across a board, not across a room.
- RS-232: the classic serial port. Levels are inverted and much larger: a 1 is a negative voltage of 3 to 15 V, a 0 a positive one. A transceiver chip converts between logic level and RS-232. It reaches a few metres at moderate baud rates.
- RS-485: each bit is the difference between two wires of a twisted pair, which rejects noise picked up equally on both. It reaches hundreds of metres and allows many devices on one pair, taking turns to transmit (half duplex). Industrial buses such as Modbus run over it.
The frame format is the same on all three; only the voltages, the wiring and the transceivers change.
Quick Check
Q: A microcontroller's UART pins are connected directly to a PC's RS-232 port. What happens?
Show Answer
It does not work and may damage the microcontroller: RS-232 levels are inverted and reach plus or minus 15 V. A level shifter such as an RS-232 transceiver is needed in between.
Running It in ChipVerify Lab
The example runs the parity test and the CTS pause. Move the noise pulse to another bit and watch the parity flag.
Common Mistakes
Mistake #1: Trusting parity too much
Parity misses every even number of flipped bits. For anything important, add a checksum or CRC at the message level.
Mistake #2: Deasserting RTS too late
The sender finishes the frame it is sending, and may have more in a FIFO behind its pins. A receiver that waits until its buffer is completely full loses bytes.
Mistake #3: Mixing up RTS and CTS wiring
RTS of one side goes to CTS of the other, just like TX and RX. Wiring RTS to RTS leaves both sides waiting.
Practice Exercise
Challenge: Two Flipped Bits
Add a second 40 ns noise pulse, one bit time after the first, so that data bits 3 and 4 of 0x55 are both flipped. Does parity catch it?
Hint
Flipping two bits changes the number of ones by 0 or 2.
Solution
flip = 1;
#40 flip = 0;
#120 flip = 1; // a second flip, one bit later
#40 flip = 0;
1795 tx sends 0x55 3525 rx got 0x4d
0x55 arrives as 0x4D with no error flag. Bits 3 and 4 changed (0 to 1 and 1 to 0), the number of ones stayed even, and the parity check passed. This is exactly the case a CRC is for.
Open the ready-made example in the lab and run the simulation.
Summary
- Even or odd parity adds one bit per frame and detects any odd number of flipped bits.
- Parity cannot locate or correct errors and misses even numbers of flips.
- RTS/CTS lets a receiver pause the sender between frames; XON/XOFF does the same in-band.
- RS-232 uses inverted, high-voltage levels; RS-485 uses a differential pair for long, multi-drop links.
- The UART frame is the same on every physical layer.
