AXI Burst Types: FIXED, INCR and WRAP

An AXI master sends only the first address of a burst. The slave works out the rest from three fields: the burst length (AxLEN), the beat size (AxSIZE) and the burst type (AxBURST), which is FIXED, INCR or WRAP. This article explains each type, the rules that limit bursts, including the 4 KB boundary, and the address calculation a slave has to implement.

9 min read | Intermediate

What You'll Learn

• Decode AxLEN, AxSIZE and AxBURST
• Calculate the beat addresses of FIXED, INCR and WRAP bursts
• Apply the burst rules: lengths, alignment and the 4 KB boundary
• Implement the next-address calculation in Verilog

Length and Size

The burst length is AxLEN + 1 beats. In AXI4, AxLEN is 8 bits, so an INCR burst can have 1 to 256 beats. FIXED and WRAP bursts are limited to 16 beats, and a WRAP burst must have 2, 4, 8 or 16.

The beat size is 2 to the power AxSIZE bytes:

The size may not be larger than the data bus. A size smaller than the bus is a narrow transfer, which uses only some of the byte lanes; see Write Strobes and Unaligned Transfers.

The Three Burst Types

For a WRAP burst, the block size is the beat size times the number of beats, and the block is aligned to that size. The specification calls its lowest address the wrap boundary. A WRAP burst of four words starting at 0x0A8 uses the 16-byte block 0x0A0 to 0x0AF, so it runs 0x0A8, 0x0AC, then wraps to 0x0A0 and 0x0A4. The start address of a WRAP burst must be aligned to the beat size.

The Burst Rules

• 4 KB boundary: a burst must not cross a 4 KB address boundary. This keeps a burst from crossing from one slave into the next (slave address regions are laid out in units of 4 KB) and limits how many address bits a slave must increment. It is the AXI version of AHB's 1 KB rule.
• No early termination: once started, a burst runs for all its beats. A master that wants to stop writing early can drive the remaining write strobes low; a master that wants fewer read beats must still accept them all.
• WRAP lengths: 2, 4, 8 or 16 beats, with an aligned start address.
• Long INCR bursts may be split into shorter bursts by an interconnect, for example to keep latency low for other masters, as long as the result is equivalent.

The Address Calculation

The specification gives the address of every beat in terms of the start address, the number of bytes per beat and the burst length. In Verilog it fits in one function, used by the slave for both reads and writes:

function [11:0] next_addr(input [11:0] a, input [2:0] size, input [1:0] burst, input [7:0] len);
  reg [11:0] bytes;
  reg [11:0] incr;
  reg [11:0] wrap_bytes;
  begin
    bytes = 12'd1 << size;
    incr  = (a & ~(bytes - 12'd1)) + bytes;           // aligned address + size
    if (burst == FIXED) begin
      next_addr = a;
    end
    else if (burst == WRAP) begin
      wrap_bytes = bytes * (len + 12'd1);              // the wrap boundary block
      next_addr  = (a & ~(wrap_bytes - 12'd1)) | (incr & (wrap_bytes - 12'd1));
    end
    else begin
      next_addr = incr;
    end
  end
endfunction

Two details matter. The increment is applied to the aligned address, so an unaligned first beat is followed by an aligned second beat. And for WRAP, the upper address bits stay those of the wrap boundary while the lower bits count around the block.

The Simulation

The testbench writes three four-beat bursts of words, one of each type. The memory slave has a trace option that prints the address of every beat it handles:

write(1, 12'h080, 3, WORD, FIXED, 32'hF0, 0, 0, 0);  // 4 beats, all to 0x080
write(1, 12'h090, 3, WORD, INCR,  32'h90, 0, 0, 0);  // 0x090, 0x094, 0x098, 0x09C
write(1, 12'h0A8, 3, WORD, WRAP,  32'hB0, 0, 0, 0);  // 0x0A8, 0x0AC, 0x0A0, 0x0A4
read(1, 12'h080, 0, WORD, INCR, 0, 30);
read(1, 12'h0A0, 3, WORD, INCR, 0, 0);

45      slave: write beat at 0x080, WSTRB 1111
55      slave: write beat at 0x080, WSTRB 1111
65      slave: write beat at 0x080, WSTRB 1111
75      slave: write beat at 0x080, WSTRB 1111
105      slave: write beat at 0x090, WSTRB 1111
115      slave: write beat at 0x094, WSTRB 1111
125      slave: write beat at 0x098, WSTRB 1111
135      slave: write beat at 0x09c, WSTRB 1111
165      slave: write beat at 0x0a8, WSTRB 1111
175      slave: write beat at 0x0ac, WSTRB 1111
185      slave: write beat at 0x0a0, WSTRB 1111
195      slave: write beat at 0x0a4, WSTRB 1111
...
355  R   id=1 data=0x000000f3 OKAY last
365  R   id=1 data=0x000000b2 OKAY
375  R   id=1 data=0x000000b3 OKAY
385  R   id=1 data=0x000000b0 OKAY
395  R   id=1 data=0x000000b1 OKAY last

The FIXED burst wrote all four beats to 0x080, so only the last value, 0xF3, remains. The WRAP burst started at 0x0A8, so its first beat (0xB0) is at 0x0A8 and its third (0xB2) at 0x0A0: an INCR read of the block returns 0xB2, 0xB3, 0xB0, 0xB1.

Running It in ChipVerify Lab

The example runs these bursts with the slave trace on. Change the start address of the WRAP burst and predict the beat addresses before you run it.

Common Mistakes

write(1, 12'h0B6, 7, HALF, WRAP, 32'hC0, 0, 0, 0);

165      slave: write beat at 0x0b6, WSTRB 1100
175      slave: write beat at 0x0b8, WSTRB 0011
185      slave: write beat at 0x0ba, WSTRB 1100
195      slave: write beat at 0x0bc, WSTRB 0011
205      slave: write beat at 0x0be, WSTRB 1100
215      slave: write beat at 0x0b0, WSTRB 0011
225      slave: write beat at 0x0b2, WSTRB 1100
235      slave: write beat at 0x0b4, WSTRB 0011