Interview Question Bank

IDs let a master have many outstanding transactions and let the system return them out of order. Transactions with the same ID must complete in the order they were issued. Transactions with different IDs have no ordering relationship, so a fast slave can return its response before a slow slave that was addressed first.

Interconnects usually extend the ID with extra bits that identify the master, so that responses can be routed back. In AXI4, write data interleaving between different IDs was removed, so the W channel has no ID.

Read more on AXI Transaction IDs and Ordering.

• FIXED: every beat uses the same address, used for FIFOs.
• INCR: the address increments by the transfer size each beat, used for normal memory.
• WRAP: the address increments but wraps at a boundary equal to the burst length times the transfer size, used for cache line fills that start at the critical word.

For example, a WRAP burst of 4 words (4 bytes each) starting at 0x34 has a 16-byte wrap boundary, so the addresses are 0x34, 0x38, 0x3C, 0x30. An AXI burst must also not cross a 4 KB address boundary.

Read more on AXI Burst Types.

SLVERR (slave error) means the transaction reached a slave, but the slave reported an error, for example an unsupported access size or a write to a read-only location. DECERR (decode error) means no slave exists at the address, and it is usually generated by the interconnect's default slave.

The difference helps software and debug: DECERR points to a wrong address or address map, SLVERR to a problem with the access itself.

Read more on AXI Responses and Exclusive Access.

AXI4-Lite is a subset of AXI4 with the same five channels but no bursts (every transaction is one beat), no IDs, no exclusive accesses, and a data width of 32 or 64 bits. Every transaction is in order.

It is used for control and status registers, where bandwidth does not matter and a simple slave design is more important. Full AXI4 is used for memory and high-bandwidth data paths, and AXI4-Stream for data streams with no addresses.

Read more on AXI4-Lite.

A skid buffer is a small two-entry buffer used to register a VALID/READY interface without losing data or bandwidth. If READY is simply registered, the upstream side only learns about back-pressure one cycle late and may send one more beat. The skid buffer catches that extra beat in a spare register.

It lets a pipeline stage break the combinational READY path for timing while still accepting one transfer per cycle.

Read more on AXI-Stream FIFO and Skid Buffer.

An idle UART line is high. A frame starts with a start bit (low), then 5 to 9 data bits sent LSB first, an optional parity bit, and one or more stop bits (high). The receiver detects the falling edge of the start bit and samples each bit near its middle, usually with a 16x oversampling clock.

Because the receiver resynchronizes on every start bit, the error only accumulates within one frame. For a 10-bit frame, the sample point of the last bit must stay within about half a bit, which gives a total mismatch budget of roughly 5 %, usually shared between transmitter and receiver.

Read more on How UART Works.

CPOL sets the idle level of the clock: 0 means SCLK idles low, 1 means it idles high. CPHA sets which edge samples the data: with CPHA 0, data is sampled on the first (leading) clock edge and changes on the second; with CPHA 1, data changes on the first edge and is sampled on the second.

The four combinations are SPI modes 0 to 3. Master and slave must use the same mode, otherwise data is sampled on the wrong edge and appears shifted by one bit.

Read more on How SPI Works.

SDA and SCL are open drain with pull-up resistors, so any device can pull a line low but none drives it high. This allows many devices on two wires without bus contention, lets a slave stretch the clock by holding SCL low, and makes arbitration possible.

START is SDA falling while SCL is high, and STOP is SDA rising while SCL is high. Normal data only changes while SCL is low. During arbitration, two masters transmit at once and each reads SDA back: a master that sends a 1 but sees a 0 has lost and stops, while the winner continues without its message being corrupted.

Read more on How I2C Works and I2C Arbitration.

1. Floorplan: die and core size, I/O pins, macro placement, rows and blockages.
2. Power planning: rings, straps and rails, plus tap and endcap cells.
3. Placement: global placement, timing-driven repair, legalization and detailed placement.
4. Clock tree synthesis: build the clock network and fix hold.
5. Routing: global routing, then detailed routing, then post-route optimization.
6. Sign-off: parasitic extraction and STA at all corners, DRC, LVS, antenna, IR drop and electromigration, then GDSII stream-out.

Read more on The RTL-to-GDSII Flow.

• The gate-level netlist from synthesis.
• Timing constraints (SDC).
• The technology LEF: routing layers, directions, pitches, widths, spacings and vias.
• The cell LEF: each cell's size, pins and obstructions.
• Liberty timing and power libraries for each corner.
• Parasitic extraction rules, and the DRC and LVS rule decks from the PDK.

The LEF files only describe what the tools need for placement and routing; the real transistor layout of each cell is in its GDS, which is merged at stream-out.

Read more on Physical Design Inputs and Outputs.

Utilization is the fraction of the core area covered by standard cells and macros. A low utilization wastes area and makes wires longer. A high utilization leaves too little room for buffers added during optimization and for routing, which leads to congestion and timing problems.

Typical starting points are 50 to 70 %, lower for designs with heavy routing such as crossbars, higher for regular datapaths. The right value is found by trying the flow and looking at congestion and timing after placement and routing.

Read more on Die, Core and Utilization.

• Place macros near the edges or corners of the core, leaving the centre for standard cells.
• Orient macro pins toward the logic they connect to, and keep macros that talk to each other close.
• Leave channels between macros wide enough for routing and power, and add halos or blockages around them.
• Follow the data flow of the design, guided by the connectivity between macros, I/Os and logic.

Poor macro placement shows up later as congestion near the macros, long wires and timing violations that placement cannot fix.

Read more on Macro Placement.

Standard cells connect to thin metal 1 rails along each row. Those rails have high resistance over long distances and need to be fed from somewhere. Straps on upper, thicker layers distribute the current across the core with low resistance, and connect to the rails through via stacks at regular intervals.

Without enough straps, the voltage drop along the rails (IR drop) slows down cells far from the supply, and the current density in thin wires can exceed electromigration limits.

Read more on Rails, Rings and Straps.

Tap cells connect the n-well to VDD and the substrate to VSS at regular intervals, which prevents latch-up in libraries whose cells do not have their own well ties. Endcap cells sit at the ends of each row to terminate the wells and diffusion properly and meet design rules at the row boundary.

Decap cells are capacitors between VDD and VSS placed in empty space. They supply charge locally when many cells switch at once and reduce dynamic voltage droop.

Read more on Tap Cells, Endcaps and Decaps.

Global placement spreads cells over the core to minimize total wire length, while limiting the density in each region, so the cells overlap and are not yet on legal sites. Timing-driven and congestion-driven placement adjust the result to shorten critical nets and avoid crowded areas.

Legalization then snaps every cell onto a row site with no overlaps, moving each cell as little as possible, and detailed placement swaps and shifts neighbouring cells to improve wire length further. Buffering and sizing repair are run in between to fix slew, capacitance and timing.

Read more on Global Placement and Legalization and Detailed Placement.

• Deliver the clock to every sink with low skew between related flops.
• Keep the insertion delay (latency) reasonable.
• Meet maximum transition and capacitance limits on the clock nets.
• Keep clock power and area low, since the clock tree toggles every cycle.

The tree is built from clock buffers or inverters, often with non-default routing rules (wider spacing, shielding) to reduce crosstalk and variation.

Read more on Why Clock Trees and CTS in OpenROAD.

Before CTS the clock is ideal: it arrives at every flop at the same time, so the skew used in the hold check is only an estimate. Hold violations depend strongly on the real skew between launching and capturing flops.

After CTS the real clock tree delays are known, so hold can be measured correctly and fixed with delay buffers where needed. Fixing hold before CTS would insert buffers against a skew that does not exist yet.

Read more on Skew, Useful Skew and Hold.

Global routing divides the chip into a grid of tiles and plans which tiles each net passes through, balancing demand against the available tracks. It reports congestion as overflow where demand exceeds capacity.

Detailed routing then assigns exact tracks, wires and vias inside each tile while obeying all spacing and width rules. Zero global overflow does not guarantee a clean detailed route, because local pin access and design rules can still cause violations.

Read more on Global Routing and Congestion and Detailed Routing.

During manufacturing, metal layers are etched with plasma, which collects charge on exposed wires. If a long wire connects only to a transistor gate before the higher layers that link it to a diffusion are built, the charge can discharge through the thin gate oxide and damage it. The antenna ratio is the wire area connected to a gate compared with the gate area.

Fixes are to jump to a higher metal layer near the gate so the long segment is connected later, to add an antenna diode that gives the charge a safe path, or to insert a buffer to split the net.

Read more on The Antenna Effect.

Before routing, wire delays are estimated from the placement, usually with simple wire models. After routing, the real wires are extracted with their resistance, capacitance and coupling, which usually makes paths slower and can add crosstalk delay.

This is why slack is often worse after routing and why post-route optimization exists. Large differences between estimated and extracted timing point to detours from congestion, long nets or missing constraints during placement.

Read more on Parasitics After Routing and Post-Route STA.