Interview Question Bank

If the functional coverage is 100% but the code coverage is too low, it typically means that there are parts of the code that are never executed and therefore not covered by the test cases. Here are some possible approaches to improve code coverage:

1. Review the code and identify the uncovered areas: You can go through the code manually or use a code coverage tool to identify the parts of the code that are not covered by the tests. This will help you to focus on the areas that need to be tested more thoroughly.
2. Add new test cases: Once you have identified the uncovered areas, you can add new test cases to cover them. You can use different techniques such as random testing, directed testing or assertion-based testing to create new test cases.
3. Modify existing test cases: You can also modify the existing test cases to cover the uncovered areas. For example, you can change the parameters or stimuli of the test cases to target specific areas of the code.
4. Use code coverage metrics: You can use code coverage metrics as a guide to track your progress and ensure that you are improving overall coverage. You can set targets for specific types of coverage, such as branch or statement coverage, and monitor your progress as you add new test cases or modify existing ones.
5. Use techniques like coverage-driven verification and constrained-random testing: These techniques focus on generating test cases to cover specific portions of the design, which can help you achieve better code coverage.

Assertions are statements that specify a particular relationship between two or more signals or variables. There are two main types of assertions, which are as follows:

1. Immediate assertion: Checks whether a particular condition is true at a particular point in time.
2. Concurrent assertion: Checks whether a particular condition is always true over a period of time.

Read more on SystemVerilog Assertions.

Array manipulation functions can be used to query indices and values in SystemVerilog arrays.

module tb;
  int   fruit_hash [string];
  string 	idx_q [$];
  
  initial begin
    fruit_hash["apple"] = 5;
    fruit_hash["pear"]  = 3;
    fruit_hash["mango"] = 9;
    
    idx_q = fruit_hash.find_index with (1);
    $display("idx_q= %p", idx_q);
  end
endmodule

// Output
// idx_q= '{"apple", "mango", "pear"} 

Read more on SystemVerilog Array Manipulation.

The function must return a value that can be used in the constraint expression. Here's an example:

function int rand_range(int a, b);
    return (a + b) % 2;
endfunction

class ABC;
    rand bit my_val;
   
    constraint my_val_c {
        my_val == rand_range(a, b);
    }
endclass

Pass-by-value and pass-by-reference are two ways of passing arguments to a function or a method in programming languages.

In pass-by-value method, a copy of the value of the argument is passed to the function or method. Any change made to the value inside the function or method does not affect the original value of the argument.

function void abc(int a, b);

In pass-by-reference method, a reference to the memory location of the argument is passed to the function or method. Any changes made to the value inside the function or method will affect the original value of the argument.

function void abc(ref int a, b);

Read the example in SystemVerilog Functions.

The initial block is executed at the start of simulation, i.e. at time 0 units. This is useful for initializing variables and stting up initial configurations. This is the very basic procedural construct supported since the first version of Verilog.

However, the final block was introduced in SystemVerilog and is executed just before the simulation ends. This does not consume any time and hence is very ideal to do last minute housekeeping tasks and print reports.

The default value of all 2-state variables are zero, and 4-state variables are X. Inputs that are not connected are Z.

Read more on SystemVerilog Data Types.

Polymorphism is a fundamental concept in object-oriented programming that allows objects of different classes to be treated as if they are objects of the same class.

The advantages of polymorphism in object-oriented programming are:

1. Code reusability: Polymorphism enables code reuse, as objects of different classes can be treated as if they are objects of the same class. This means that common behaviors and methods can be defined in a superclass and inherited by multiple subclasses.
2. Flexibility and extensibility: Polymorphism allows objects to behave differently based on the context in which they are called, improving the flexibility of the code. It also enables extensibility by allowing new subclasses to be added to a program easily without modifying the existing code.
3. Code readability and maintainability: Polymorphism can improve the readability and maintainability of the code by reducing the amount of redundant code and making it easier to understand the relationship between different classes.

Read the examples in SystemVerilog Polymorphism.

The this keyword is used to explicity reference the current class object. This is mostly used within class definitions to be able to specifically reference variables and methods belonging to the same class.

Read more on SystemVerilog 'this' keyword.

SystemVerilog interfaces are a way to create structured hierarchical connections between modules and blocks in a design. They provide a way to bundle signals and functionality into reusable components, which can be easily instantiated and connected in a design.

1. Modular design: Interfaces provide a modular approach to design, making it easier to create and reuse building blocks in a system.
2. Encapsulation: They help in encapsulating the functionality and signals inside a module or block, making it easier to understand and maintain.
3. Configurability: Interfaces can be parameterized, allowing for easy configurability and scalability.

Read more on SystemVerilog Interface.

Both reg and logic are used to store 4-state logic values that can be referenced later. The main difference is that logic signals can be used in both procedural and continuous assignments whereas reg can only be used in procedural code.

Read more on SystemVerilog logic datatype.

Both operators are used in distribution constraints to assign weightage to different values in the distribution.

The :/ operator assigns the specified weight to the item, or if the item is a range, then the weight of each value is divided by N. The := operator assigns the specified weight to the item or if the item is a range, then to every value value in the range.

Read more on SystemVerilog Constraint Examples.

Randomization of variables can be disabled with rand_mode.

class ABC;
	rand bit [3:0] data;
endclass

module tb;
	initial begin
		ABC m_abc = new;
		m_abc.data.rand_mode(0); 	// Disable randomization
		
		m_abc.data.rand_mode(1); 	// Enable randomization
	end
endmodule

Code coverage is a metric used to measure how well tests have exercised the design under test. It typically reports on the percentage of execution achieved across various dimensions of the design, such as statements, branches, and expressions, toggle, assertions and FSM.

Read more on Code Coverage.

Here's an example constraint that detects odd numbers of ones in an 8-bit sequence:

class ABC;
  rand bit [7:0] data;

  constraint c_data { $countones(data) % 2 != 0; }
endclass

module tb;
  initial begin
    ABC m_abc = new;

    for (byte i = 0; i < 20; i++) begin
      m_abc.randomize();
      $display("data = 0b%0b", m_abc.data);
    end
  end                             
endmodule

A class member declared as local is available only to methods inside the class and are not visible within subclasses.

A class member declared as protected is available to methods inside the class and also to methods within subclasses.

Read an example in SystemVerilog local qualifier.

1. Modular Design: Each module/class represents different aspects of the design. As a result, it becomes easier to develop a test bench by reusing and integrating these modular components. This saves time and effort in developing test cases and makes the system more scalable.
2. Encapsulation: Operations performed on any data object can be defined within the same class. For example, a function to pack a data array into a stream of 64 bit data.
3. Inheritance: Allows to create a base class and extend it with further derived classes. Common properties and methods are usually defined in base classes so that all subclasses have access and hence avoid code duplication
4. Polymorphism: Allows different implementations of the same method or function. Polymorphism helps to implement alternate test case scenarios without affecting the rest of the code significantly.

Read more on SystemVerilog Inheritance and Polymorphism.

An interface is a collection of signals that allow connections to the DUT from the testbench. The handle to this interface is made available in classes by making it virtual. Hence a virtual interface is nothing but a handle that can hold a reference to the actual interface. Remember that an interface is declared at the testbench top level so that it can be passed to the DUT. So, rest of the components get access to this interface via a virtual interface.

class wishbone_monitor;
	virtual wishbone_if 	m_vif; 	// A virtual interface handle

	virtual task monitor;
		forever begin
			@(m_vif.clk);
			// Rest of the code
		end
	endtask
endclass

logic is a new SystemVerilog data type, when compared to Verilog which can be used in place of reg and wire in both procedural blocks and continuous assignments. It removes the hassle of having to redefine an existing signal as reg or wire depending on where it is used.

function void push_unique(ref bit [7:0] array[$]);
	for (int i = 0; i < 10; i++) begin
		int num;
		std::randomize(num) with { num inside {[0:50]};
									!(num inside {array}); 
								};
		array.push_back(num);								
	end
endfunction