Interview Question Bank

Questions asked in RTL design, verification, timing, physical design and post-silicon interviews.

337 Questions
149 Verilog
100 SystemVerilog
15 SoC Verification
14 Formal Verification
15 Static Timing Analysis
15 Bus Protocols
15 Physical Design
14 Post-Silicon Validation

Results 141 - 160 of 337 Click a question to show its answer.

What are the testability implications for derived clocks ? Verilog ▲ 0

Derived clocks are created within a chip using clock dividers through Flip-Flops or PLLs. Because these clocks are generated internally, a control signal from the primary pins is necessary to prevent Flip-Flops from capturing data at unintended times.

A multiplexor can be added in the clock path with the select line controlled by a test mode enable signal. The inputs to the mux should be regular clock and derived clock.

From Verilog Interview Questions Set 15

What are the testability challenges of gated clocks ? Verilog ▲ 0

Gated clocks are typically used to reduce power consumption by disabling the clock signal to specific parts of the chip when they are not in use. However, during testing, it is essential to be able to access and control these signals in order to ensure correct operation of the chip and detect any faults.

The workaround is to logically OR a test mode enable signal to the enabling pin of the AND gate that gates the clock.

From Verilog Interview Questions Set 15

What is the implication of a combinatorial feedback loops in design testability? Verilog ▲ 0

Combinatorial feedback loops occur when the output of a combinational logic gate is fed back into one of its inputs, potentially creating a feedback loop that can lead to unexpected behavior or cause the design to become stuck in an unstable state. Since the loops are delay-dependent, they cannot be tested with any ATPG algorithm and must be avoided in the logic.

From Verilog Interview Questions Set 15

How does the presence of latches affect the testability ? Verilog ▲ 0

One of the main issues with latches is that they can cause the propagation of glitches, which are short-lived pulses that can be difficult to observe during testing. These glitches can be especially problematic if they propagate to other parts of the design, potentially causing unintended behavior or creating false positives during testing.

Output of a latch is not controllable directly from a primary input since, the enable to a latch is not the regular clock going to rest of the flops in the design. The enable pin to the latch needs to be OR'd with a test mode enable signal.

From Verilog Interview Questions Set 15

What value is sampled by the logic from an input port that is left open (that is, no-connect) during its module instantiation? Verilog ▲ 0

An unconnected input port is a floating port, and it may float to an intermediate voltage level due to parasitic capacitance and inductance in the circuit. In simulations, this is indicated by the value 'Z' or high impedance and logic driven by it sees an unknown: gates and most operators treat a 'Z' input as 'X', so 'X' propagates until it is masked, for example by an AND with 0.

To avoid these types of issues, it is generally recommended to tie all unused input ports to a known state, such as ground or VDD, through the use of pull-up or pull-down resistors. This can help to prevent the input signal from floating and ensure that the logic gates are working as intended.

The default value of Z can be changed using compiler directives.


// Causes all unconnected input ports following this to be pulled down to logic 0
`unconnected_drive pull0

module mod_2341( ... );
 ...
endmodule

// Do not apply for rest of the code
`nounconnected_drive

From Verilog Interview Questions Set 15

How is the connectivity established in Verilog when connecting wires of different widths? Verilog ▲ 0

Connections are right-justified, which means that the LSB of the RHS is connected to the LSB of the LHS.


wire [7:0] 	net1;
wire [3:0] 	net2;

// net2 is narrower than net1, so it is zero-extended and net1[7:4] = 0
assign net1 = net2;

// net2 gets the truncated value of net1[3:0]
assign net2 = net1;

From Verilog Interview Questions Set 15

Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type? Verilog ▲ 0

Yes, with a constant function. A constant function is called with constant arguments, such as parameters or literals, and is evaluated during elaboration, so its result can size a port, wire or reg. It must be declared in the same module and cannot use hierarchical references.


function integer clog2 (input integer value);
  begin
    value = value - 1;
    for (clog2 = 0; value > 0; clog2 = clog2 + 1)
      value = value >> 1;
  end
endfunction

parameter DEPTH = 16;
input [clog2(DEPTH)-1:0] addr;   // 4-bit address

Verilog-2005 also has a built-in $clog2 system function for this common case.

From Verilog Interview Questions Set 15

Summarize the main differences between $strobe and $monitor Verilog ▲ 0

$strobe displays values of selected signals at the end of the current simulation time when all simulation events have occurred and just before time advances whereas $monitor displays the value of selected signals whenever its value changes.

Read more on Verilog Display Tasks.

From Verilog Interview Questions Set 15

How can I selectively enable or disable monitoring? Verilog ▲ 0

This can be done with $monitoron and $monitoroff tasks.

From Verilog Interview Questions Set 15

How will you test the functionality of interrupts using functional coverage? SystemVerilog ▲ 0

Testing the functionality of interrupts using functional coverage involves the following steps:

Define functional coverage goals: First, you need to define your functional coverage goals. These goals should be specific to the interrupts you want to test. For example, you might define goals for interrupt latency, interrupt frequency, or interrupt priority handling.
Create a testbench for interrupts: Next, you need to create a testbench that generates interrupts with different characteristics. This testbench should also monitor the behavior of the design under test (DUT) in response to the interrupts.
Implement functional coverage: You can then implement functional coverage in your testbench to track how often each of the defined functional goals is achieved. You can use standard SystemVerilog constructs like covergroups, coverpoints, and bins to define and track the functional coverage.
Analyze the functional coverage results: Finally, you can analyze the functional coverage results to determine how well your testbench tests the desired interrupt functionality. Based on the results, you can make adjustments to your testbench to improve the tests.

From SystemVerilog Interview Questions Set 1

What is the use of scope resolution operator? SystemVerilog ▲ 0

The scope resolution operator in SystemVerilog is denoted by the double colon '::' symbol. The basic purpose of this operator is to specify the scope in which an identifier is defined or should be searched for.

Here are some common uses of the scope resolution operator:

Accessing a base class's members from a derived class: The :: operator can reach a superclass's public or protected members directly from a subclass, or reach anything declared static from outside the class hierarchy entirely. This is a genuinely different mechanism from the dot operator's hierarchical name referencing (e.g. top.sub.clk), which navigates module/instance hierarchy rather than class or package scope — :: only ever resolves against a class type, package, covergroup, or typedef name, never an instance path.
Resolving naming conflicts: When a design has two or more variables or modules with the same name, the scope resolution operator can be used to differentiate the variables or modules by specifying their scope.


  	package ahb_pkg;
  		typedef enum {READ, WRITE} e_access;
  	endpackage
  
  	package wishbone_pkg;
  		typedef enum {WRITE, READ} e_access;
  	endpackage
  
  	ahb_pkg::e_access 	m_access; 		// m_access = 1 indicates WRITE

Accessing static variables and functions: The scope resolution operator is also used to access static properties and methods in a class.
Accessing items in package: Elements in a package can be imported using import with scope resolution operator.


	import ahb_pkg::*; 	 		// Imports everything in the package called "ahb_pkg"
	import enum_pkg::global; 	// Imports everything under "global" from enum_pkg

From SystemVerilog Interview Questions Set 1

How do you implement randc in SystemVerilog? SystemVerilog ▲ 0

The randc keyword in SystemVerilog will first exhaust all combinations possible before repeating a value. This is different from rand keyword where the same value may repeat even before all combinations are exercised.

Here's an example :


class ABC;
	rand 	bit [1:0] 	x; 		// randomization can give x = 3, 1, 1, 0, 3, 0, 2, 2
	randc 	bit [1:0] 	y; 		// randomization can give y = 1, 3, 0, 2, 3, 1, 2, 0 
endclass

Read more on SystemVerilog rand Variables.

From SystemVerilog Interview Questions Set 1

What is inheritance? SystemVerilog ▲ 0

Inheritance is a concept in object-oriented programming that allows creating a new class by inheriting or extending the properties and behavior of an existing class. The existing class is called the parent or base class, and the new class is called the child or derived class. The child class inherits all the members of the parent class, such as variables, methods, and constructors, and can also add new members or override the inherited members.

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