Interview Question Bank

Assume memory region from 0x0 to 0x100. There is a small region in between from 0x20 to 0xE0 that is reserved. Write system verilog constraints to choose a block of memory of size 16 bytes that is outside the reserved region and inside the entire memory range. The starting address of the block should be 4-byte aligned.

rand bit [31:0] 	addr;
int 				size = 'h10;

constraint c_addr 	{ 	addr inside {[0:'h100]};      	// Ensure its within memory region
						!(addr inside {['h20:'hE0]}); 	// Ensure its not in reserved region
						addr % 4 == 0; 					// Ensure its 4-byte aligned
						addr + size inside {[0:'h20], ['hE0:'h100]}; 	// Ensure its either in lower or upper region
						!(addr + size inside {'h20, 'h100}); 		// Ensure last addr does not hit limit
					}

Assume a memory region exists from 0x2000 to 0x4000 that is byte addressable. Write SV constraints to randomly pick an address within this memory region that is aligned to 4-byte boundary.

	rand bit [31:0] 		addr;
	constraint c_addr 	{ 	addr inside {[32'h2000:32'h4000]};
							addr % 4 == 0;
						//  addr[1:0] == 0;  	Also okay
						}

Assume a class called "ABC" has been used throughout in a project. In a derivative project, you had to extend "ABC" to form "DEF" and add some more variables and functions within it. What will happen if you try to use an object of "ABC" that was created in the legacy testbench to access these new variables or functions ?

It will result in a compilation error because the new variables do not exist in the base class. Instead you need to declare a local variable of type "DEF" and perform a dynamic cast if required to access the new variables and functions.

module tb;
	initial begin
		bit [31:0] result;
		
		result = 1 << $urandom_range(3, 6);
	end
endmodule

A queue is a variable size ordered collection of elements of the same type. Read more on SystemVerilog Queues

A mailbox is a communication mechanism used by testbench components to send a data message from one to another. A mailbox has to be parameterized to hold a particular element and can be either bounded or unbounded. It can also suspend the thread by tasks like get() and put(). So a component can wait until an item is available in the mailbox. Read more on SystemVerilog Mailbox

SystemVerilog allows us to randomize variables inside a class using rand and randc constructs.

rand randomizes the variable and can have repetitive values before the entire set of allowable values are used. For example, a 2-bit variable when used with rand can give values 1, 3, 3, 2, 1, 3, 0

randc randomizes the variable and repeats a value only after the entire set of allowable values are used. For example, a 2-bit variable when used with randc can give values [1, 3, 2, 0], [0, 3, 1, 2], 1 ... The values in the square brackets show a set.

See an example Random variables

The super keyword is used to access variables and methods of the parent class and is a very basic construct of OOP.

See an example and read more on super here.

An extern keyword is used to define methods and constraints outside the class definition. For example, we could have the declaration of functions and constraints within the class body, but do the complete definition later on outside the class body.

Read more on SystemVerilog 'extern'.

Clock edges are the most probable points for a race condition to arise. The DUT may sample one value but the testbench may sample something else.

Although race conditions may arise from improper coding practices, use of SystemVerilog Clocking Blocks allows the testbench to sample DUT appropriately and drive inputs to the DUT with a small skew. Also, this allows the skews to be changed later on with minimal code change.

Race condition can also be avoided by the use of program blocks and the use of non-blocking assigments.

In SystemVerilog, a bit is a single binary digit that can have a value of 0 or 1. logic is a 4-state data type that can additionally hold X (unknown) and Z (high-impedance), so it can represent exactly four values: 0, 1, X, or Z.

Read more on SystemVerilog Data Types.

// To check if all bits of variable "xyz" are Z
if (xyz === 'Z) begin
	$display("All bits in xyz are Z");
end

// To check if any bit in "xyz" is Z
if ($countbits(xyz, 'Z)) begin
	$display("Some bit in xyz is Z");
end

// To check if signal is X
if ($isunknown(xyz)) begin
	$display("xyz is unknown or has value X");
end

Assume two base classes A and B, and two derived classes C and D where this relation between classes is unknown to end user. How do you find base class for each derived class?

class A;
class B;

// Assume this relation is hidden from end user
class C extends B;
class D extends A;

module tb;
	initial begin
		A 	m_a = new();
		B 	m_b = new();
		C 	m_c = new();
		D 	m_d = new();

		// Successful cast implies that the second arg is a child of first arg
		if ($cast(m_a, m_c))
			$display("C is a child of A");
		if ($cast(m_a, m_d))
			$display("D is a child of A");

		if ($cast(m_b, m_c))
			$display("C is a child of B");
		if ($cast(m_b, m_d))
			$display("D is a child of B");
	end
endmodule

Delays are indicated by the # construct and a random delay can be written as follows.

`timescale 1ns/1ps

module tb;
	initial begin
		int delay;

		std::randomize(delay) with { delay inside {[100:500]}; };
		#(delay) $display("Statement printed after %0d delay", delay);

		// This is also good enough, although there's no variable to print actual randomized delay
		#($urandom_range(100, 500)) $display("Some delay between 100 to 500");
	end
endmodule

parameter is used to define compile-time constants used within modules, which are values that can be evaluated and assigned before the simulation starts. It can be used to specify parameters such as width, depth, or delay of modules.

module my_module #(parameter WIDTH=8) (
    input [WIDTH-1:0] data_in, 
    output [WIDTH-1:0] data_out 
);
    // module logic here
endmodule

typedef is used to define custom data types that can be reused throughout the design. It can be used to define complex data types such as structures, arrays, and enumerated types. It is used to make the code more readable and easier to understand by encapsulating complex data types within a single type name.

typedef struct { 
    logic [7:0] addr; 
    logic [31:0] data; 
} request_t;

request_t my_req;

my_req.addr = 8'h22; 
my_req.data = 32'h12345678; 

Read more on Verilog Parameters and SystemVerilog typedef.

In SystemVerilog, solve - before is a constraint solver directive that allows constraints to be solved in a specific order. This directive specifies that a particular constraint should be solved before another constraint. It is useful in cases where certain constraints must be solved before others to avoid conflicts or to ensure that specific constraints are satisfied.

Read more on SystemVerilog solve before.

alias is a keyword used to declare an alternate name for a net — it only works on nets, not variables. It allows access to the same net through multiple names, with the new name referring to the exact same net as the original.

wire [7:0]  _byte;
wire 		_bit;

alias bits_9 = { _byte, _bit };

Read more on SystemVerilog alias.

module tb;
	bit [7:0] 	q [$];
	bit [7:0] 	tmp [$];

	initial begin
		repeat (10) q.push_back($random);
		
		for (byte i = 0; i < q.size(); i += 5)
			tmp = q[i +: 5];                                                           
	end

endmodule

Read more on SystemVerilog Queue and Verilog Part-Selects.

A clocking block is used to model clock and reset signals and their associated timing control signals. It provides a way of defining a set of timing signals as well as their phases and signal transitions.

A modport is used to group a set of port declarations into a named entity. It allows designers to specify multiple port configurations and to limit access to specific module interfaces.

$random returns signed integer values, whereas $urandom returns an unsigned integer value.

	int 	 	data1;
	bit [31:0] 	data2;

	data1 = $random; 	// signed integer
	data2 = $urandom;  	// unsigned integer

An always block is a concurrent process that runs forever and gets triggered based on changes to signals in the sensitivity list. A program block is intended to be a testcase that applies stimulus to the DUT and finish at some point in time. Having an always block will stall the program from coming to an end and hence it doesn't make sense to include it in a program block.