Loads, Stores and Addressing

Loads and stores are the only RISC-V instructions that touch memory. Every variable that does not fit in a register, every array element, every field of a structure and every device register is reached through them, and all of them compute their address the same simple way: a register plus a small constant. This article explains the load and store instructions, shows how the compiler turns C variables, arrays, pointers, structures and the stack into addresses, compares RISC-V's single addressing mode with the richer ones of other ISAs, and shows how often programs load and store and what a load costs when its result is needed right away.

14 min read | Beginner

What You'll Learn

• Use the RV32I load and store instructions and their sizes and extensions
• Explain base plus offset addressing and its range
• Trace how globals, arrays, pointers, structures and the stack become addresses
• Explain why a load followed immediately by its use costs a cycle, and how compilers avoid it

Only Loads and Stores Touch Memory

RISC-V is a load/store architecture: arithmetic instructions work only on registers, and memory is reached only through load and store instructions. To add a number in memory to a register, a program first loads it into a register, then adds. Registers and the Register File explains why: registers are fast and few, memory is large and slower, and keeping the two jobs apart makes every instruction simple.

RV32I has five loads and three stores:

There is no lwu in RV32I, because a 32-bit load already fills the whole register. Stores need no signed and unsigned variants, because they only write bits and never widen anything. The byte order inside a word is little-endian, as Memory, Addresses and Endianness explains.

One Addressing Mode: Base Plus Offset

An addressing mode is a rule for computing the address of a memory access. RISC-V has exactly one: the effective address is the value of register rs1, the base, plus a 12-bit signed constant from the instruction, the offset:

address = rs1 + sign-extended offset        offset range: -2,048 to +2,047 bytes
lw a5, 8(a4)      reads the word at a4 + 8
sw a3, -4(a4)     writes a3 to the word at a4 - 4

An offset of 0 gives plain register-indirect addressing, the address is just the register. A base of x0, which is always zero, gives absolute addressing for the lowest and highest 2 KB of the address space. Anything else, a scaled index or a larger offset, is computed with ordinary arithmetic instructions first. The same adder in the execute stage that does an add computes every address, so loads and stores need no extra address hardware.

From C Variables to Addresses

A C programmer never writes addresses explicitly for ordinary variables, but every variable that lives in memory has one, and the compiler must produce it in a register before it can load or store. Small compiled programs show each common case.

Global Variables and Arrays

A global array such as static u32 a[1024]; gets a fixed address from the linker, here 0x58. The compiler builds that address with lui and addi, then uses it as the base:

  18:  000007b7   lui   a5,0x0
  1c:  05878713   addi  a4,a5,88        # a4 = 0x58, the address of a[0]

Larger programs often reserve a register, gp (the global pointer), to point into the middle of the global data, so that any global within 2 KB of it needs just one load with a gp-relative offset. These small programs are linked without that optimization, so every global address is built explicitly.

Walking an Array: Pointers Instead of Indexes

Element a[i] of a word array is at address a + 4 x i. A literal translation of a loop over i would compute that address every time: shift i left by 2, add the base, then load. Compilers usually do something cheaper: they keep a pointer that starts at a[0] and add 4 to it in each iteration, and stop when it reaches the end. A loop that copies memory works this way with two pointers:

  60:  00062683   lw    a3,0(a2)        # load src[i]
  64:  00460613   addi  a2,a2,4         # src pointer + 4
  68:  00470713   addi  a4,a4,4         # dst pointer + 4
  6c:  fed72e23   sw    a3,-4(a4)       # store to dst[i], the word before the new pointer
  70:  feb618e3   bne   a2,a1,60        # until src reaches its end

The store uses the offset -4 because the destination pointer has already been moved on. The offset field lets the compiler place the pointer update wherever it fits best, without an extra instruction to undo it. The loop variable i has disappeared entirely: the end test compares the pointer with the end address in a1.

Structures: Fields at Fixed Offsets

A C structure places its fields one after another at fixed offsets from its start. In a linked list, each node might be struct node { struct node *next; u32 val; }: next at offset 0, val at offset 4. Walking the list is the classic pointer chasing loop:

 15c:  0047a703   lw    a4,4(a5)        # a4 = p->val   (offset 4)
 160:  0007a783   lw    a5,0(a5)        # p = p->next   (offset 0)
 164:  00e50533   add   a0,a0,a4        # s += val
 168:  fe079ae3   bnez  a5,15c          # until p is NULL

The base register holds the address of the structure, and the offset selects the field. Every field access is one instruction, which is why base plus offset is such a good fit for C. Note that the second load overwrites the register it uses as its own base: the new p is loaded from the old p.

The Stack

Local variables that do not fit in registers, and registers that a function must preserve, go on the stack, a region of memory addressed through the stack pointer sp. The main function of a linked-list program starts by making room and saving registers:

  18:  fe010113   addi  sp,sp,-32       # allocate 32 bytes of stack
  20:  00812c23   sw    s0,24(sp)       # save s0 at sp + 24
  34:  00112e23   sw    ra,28(sp)       # save the return address at sp + 28
  ...
 174:  01c12083   lw    ra,28(sp)       # restore before returning
 18c:  02010113   addi  sp,sp,32        # free the stack space

Every stack access is base plus offset with sp as the base. How a Program Runs: Loops, Calls and the Stack explains why functions save registers and how the stack grows and shrinks.

Device Registers

Devices are reached the same way: build the device's address in a register, then load or store with an offset. A small test program might end with lui t0, 0xf0000 followed by sw a0, 0(t0), a store to a device register at 0xF000_0000 that reports its result.

Alignment in Practice

A word access is aligned when its address is a multiple of 4, a halfword access when its address is a multiple of 2. RISC-V lets each processor decide what to do with a misaligned access: handle it in hardware, possibly slowly with two memory accesses, or raise a misaligned-address exception and let software handle it. Small cores usually expect aligned accesses, because supporting misaligned ones means splitting an access across two memory words and joining the halves.

Compilers make sure ordinary C code never produces misaligned accesses. Every variable is placed at an address that is a multiple of its size, and inside structures the compiler inserts unused padding bytes where needed. In struct { u8 tag; u32 value; }, value cannot start at offset 1; the compiler puts it at offset 4, leaves bytes 1 to 3 unused, and the structure takes 8 bytes instead of 5. Reordering the fields from largest to smallest often removes padding, which matters for large arrays of structures.

Misaligned accesses appear when software reinterprets raw bytes, for example reading a 32-bit length field at byte offset 3 of a received network packet through a cast pointer. Portable code copies such fields byte by byte, or with memcpy, so that the compiler can generate accesses that are safe on any processor.

Richer Addressing Modes Elsewhere

Other ISAs offer more ways to form an address. x86 allows base + index x scale + displacement in a single instruction, so a[i] with i in a register is one access. Arm has modes that update the base register automatically after the access (post-increment), which turns the memcpy loop's pointer updates into part of the load and store. x86 even lets arithmetic instructions read memory directly, such as adding a memory word to a register in one instruction.

Richer modes mean fewer instructions, but more complex hardware: an address unit that shifts and adds three values, loads that also write a second register, instructions of variable length. RISC-V chose the opposite trade. Its one mode needs only the existing adder, every load writes exactly one register, and the compiler's pointer tricks recover most of the instruction count. The consequences of such choices are the subject of ISA Design Choices: RISC, CISC and Extensions.

How Often Programs Load and Store

In one test of six small programs, every executed load and store was counted. The share varied widely, from almost half for a sort that constantly moves data to about 3 percent for a checksum that keeps its working values in registers. Adding up an array came to a quarter, and copying memory to about a fifth. Across typical integer programs, loads and stores together are often a quarter to a third of all instructions, which is why the memory system matters so much for performance.

When the Loaded Value Is Needed Right Away

In a pipelined processor, a load delivers its data later than an arithmetic instruction delivers its result: the data only arrives after the memory access stage. If the very next instruction needs the loaded value, it must wait, usually one cycle in a five-stage pipeline. This one-cycle bubble is a load-use stall. The bubble sort's comparison is a textbook case:

  64:  0007a703   lw    a4,0(a5)        # a[j]
  68:  0047a683   lw    a3,4(a5)        # a[j+1]
  6c:  00e6f663   bgeu  a3,a4,78        # needs a3 immediately: one stall cycle

Sorting 64 values this way compares 63 + 62 + ... + 1 = 2,016 pairs, and one test confirmed exactly one stall per comparison. A pointer-chasing loop over a linked list, by contrast, had none, although each node's address comes from the previous load: the compiler placed the add between the load of next and the branch that tests it, and loaded val one instruction ahead of its use. Arranging instructions so that a loaded value is not needed immediately is called instruction scheduling, and compilers do it routinely. The Pipelining chapter explains the stall in detail.

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