Computer architecture interviews test whether you can reason about a processor, not whether you can recite definitions. Interviewers usually start with a basic idea, then push on it: what happens at the limit, how would you measure it, what does it cost? This article collects the questions that come up most often in interviews for CPU design, verification, performance and SoC roles, with worked answers. It also shows how to approach a question you haven't seen before.
12 min read | Intermediate
What You'll Learn
- Answer the most common questions on pipelines, hazards and branches
- Work through cache, memory and virtual memory calculations
- Explain out-of-order execution, coherence and consistency clearly
- Use a method for questions you have not seen before
How to Answer
A good answer has a shape. State the idea in a sentence. Give a small concrete example. Then say what it costs, or when it fails. For a numerical question, write down the formula first, and state any assumptions out loud. If you don't know something, say what you do know, and reason from there: interviewers are often more interested in how you think than in whether you remember one detail.
Three questions apply to nearly anything: what's the common case, what does it cost in area, power and time, and how would you measure it? Saying these out loud shows an architect's way of thinking.
Performance
What is the performance equation? Run time = instruction count x CPI x clock period. The instruction count depends on the program, compiler and ISA, CPI on the microarchitecture and program, and the period on the microarchitecture and technology. See The Performance Equation.
Why is clock frequency a poor measure of speed? It ignores CPI and instruction count. A deep pipeline can run at a higher clock with a worse CPI and finish later. Different instruction sets also do different amounts of work per instruction.
State Amdahl's law and give an example. Speedup = 1 / ((1 - f) + f / s). If 40 percent of a program gets 5 times faster, the speedup is 1 / (0.6 + 0.08) = 1.47, and the limit is 1 / 0.6 = 1.67. The unimproved part sets the limit.
Why use the geometric mean for benchmark ratios? It gives the same ranking whichever machine is the reference. The arithmetic mean of ratios can make each of two machines seem faster than the other.
Pipelines and Hazards
What are the five stages of a classic pipeline? Fetch, decode with register read, execute, memory access, and write back. Pipeline registers between the stages hold each instruction's data and control signals.
Name the kinds of hazard. Structural: two instructions need the same hardware. Data: an instruction needs a result that isn't ready. Control: the next PC isn't known yet.
What is forwarding, and what can't it fix? It passes a result from a later pipeline register straight to the ALU inputs, so that a dependent instruction needn't wait. It can't fix a load followed at once by its use, because the data doesn't exist until the end of MEM. That needs one stall, as Load-Use Stalls and Control Hazards explains.
Show the forwarding priority. If EX/MEM and MEM/WB both write the register needed, take EX/MEM, as it is the newer. Also check for a write enable, and that the register isn't x0.
Why not make the pipeline 100 stages? Register overhead stops frequency from rising in proportion, and branch mispredictions and hazards cost more with each stage. Power rises as well. Performance peaks at a depth well below that, as Pipeline Depth vs Frequency shows.
Quick Check
Q: A five-stage core has a base CPI of 1, 20 percent loads with a quarter followed at once by a use, and 15 percent taken branches, costing 2 cycles. What is its CPI?
Show Answer
1 + 0.20 x 0.25 x 1 + 0.15 x 2 = 1 + 0.05 + 0.30 = 1.35.
Branch Prediction
Why do branches hurt? The processor must fetch before it knows the outcome, so it guesses, and each wrong guess flushes work. The cost per instruction is branch rate x miss rate x penalty.
Why is a two-bit counter better than one bit? A one-bit predictor mispredicts twice per loop, at the exit and on re-entry. A two-bit counter stays on "taken" after one surprise, so it mispredicts once.
What is a BTB? A return address stack? A BTB caches branch targets by PC, so that a taken branch costs no cycle. A return stack pushes on each call and pops on each return, because returns change target with each caller, which a BTB can't handle.
How does gshare work? It XORs the PC with a global history of recent outcomes, to index a table of two-bit counters. This lets one branch use different counters depending on the recent path, so that it can learn patterns and correlations. See Dynamic Predictors: Bimodal and gshare.
Caches
Split an address. For a 32 KB, 4-way cache with 64-byte lines and 32-bit addresses: offset 6 bits, sets = 32,768 / 64 / 4 = 128, so index 7 bits, and tag 32 - 7 - 6 = 19 bits.
What are the three Cs? Compulsory: the first touch. Capacity: the working set doesn't fit. Conflict: too many blocks map to one set. Associativity fixes only the last.
Write-through or write-back? Write-through updates memory on each store, which is simple, and uses a write buffer. Write-back updates memory only on eviction, using a dirty bit, which cuts traffic, but adds complexity.
What is AMAT? Hit time + miss rate x miss penalty. With two levels, the L1 penalty is the AMAT of L2. Example: 1 + 0.05 x (10 + 0.4 x 100) = 3.5 cycles.
What's LRU, and when does it fail? It evicts the line unused the longest. It fails when a loop cycles through just more lines than fit, because each access evicts the next one needed. Random replacement does better in that case.
Why are L1 caches split? The pipeline needs an instruction and data in the same cycle, so two ports are needed, and two small caches can be placed for the best timing next to their pipeline stages.
Virtual Memory
Why have virtual memory? Protection between processes, relocation, simple allocation, and running more than fits in memory.
What does a TLB do? What's the difference between a TLB miss and a page fault? A TLB caches translations. A TLB miss means the translation isn't cached, and hardware walks the page table. A page fault means the table has no valid entry for this access, and the OS handles it. See TLBs and Page Table Walks.
What is VIPT, and what limits it? Index with the page offset bits, and compare physical tags, so that lookup and translation run in parallel. One way can't exceed one page, which is why 32 KB, 8-way L1 caches are so common with 4 KB pages.
How many levels does a page table need? Sv32: 2 levels, 10 + 10 bits plus a 12-bit offset. Sv39: 3 levels of 9 bits each. A flat table for 32 bits would be 4 MB per process, mostly empty.
Quick Check
Q: A 64-entry TLB with 4 KB pages misses often on a 1 GB array. What's the simplest fix?
Show Answer
Use large pages. The reach of 64 entries at 4 KB is 256 KB, far less than 1 GB, whereas at 2 MB it is 128 MB. Adding entries helps much less than raising the page size.
Traps and Privilege
What's a precise exception? All earlier instructions have finished, and the faulting one and all later ones have had no effect, so that software can fix the problem and restart.
How does a pipeline keep exceptions precise? It records a fault in the pipeline register, and takes it only at a commit point, in order. Out-of-order cores use a reorder buffer for the same purpose.
What happens on a trap in RISC-V? Hardware saves the PC in mepc, the cause in mcause, disables interrupts, records the previous mode, and jumps to mtvec. The handler saves registers, and mret reverses it. See Traps and Precise Exceptions.
Out-of-Order Execution
Why go out of order? To run instructions when their inputs are ready, rather than letting one stalled instruction hold up the rest.
What does register renaming do? It maps architectural registers to a larger set of physical registers, which removes false dependences (write-after-read and write-after-write). True dependences stay.
What's the reorder buffer for? It holds in-flight instructions in program order, and commits them in order, which gives precise exceptions and recovery from mispredictions.
How can a load pass a store? It speculates that they don't overlap. A load queue checks when the store's address is known, and on a conflict the load and everything younger are flushed. A predictor learns which loads to hold back.
Multicore
What's the difference between coherence and consistency? Coherence: all cores agree on the order of writes to one location. Consistency: the rules on how writes to different locations appear to other cores.
Describe MESI. Modified: the only copy, changed. Exclusive: the only copy, clean. Shared: clean, maybe several copies. Invalid. E avoids a message for private data, since a write can go from E to M silently. See Cache Coherence Protocols.
What's false sharing? Two threads write different variables in one cache line, which bounces between cores. The fix is to put them in separate lines.
What's the store buffering test? Each core stores to one variable and then loads the other. On real hardware both loads can see 0, because stores wait in a buffer. A fence prevents it.
How would you build a lock? An atomic swap in a loop, with acquire ordering, and a release store. On RISC-V, amoswap.w.aq or an lr/sc pair.
Where Does This Matter?
Interview style varies with the role. A design role may ask you to sketch a FIFO or a forwarding unit in Verilog. A verification role may ask how you would test a cache or find a bug in a pipeline. A performance role may give you a CPI stack and ask what to fix first. Many interviews include one open-ended design question, such as "design a branch predictor for this core", in which your questions about the workload count as much as your answer.
Approaching an Unknown Question
Suppose you are asked "design a cache for a video decoder". A useful way in:
- Ask about the workload. Does it access memory in order? How much data? What are the deadlines?
- State the goal and the limits: performance, area, power.
- Propose something simple, with numbers.
- Work out its cost, using AMAT or the performance equation.
- Name the risks, and how you'd measure them.
Video reads frames in order, so spatial locality is high, and a next-line prefetcher helps a great deal, with long lines. Real-time deadlines mean that the worst case matters. You may reach this answer even if you've never designed such a cache, simply by following the steps.
Common Mistakes
Mistake #1: Reciting a definition and stopping
Add an example, and a cost. "A BTB stores branch targets" is a definition. "A BTB saves two cycles per taken branch for a few hundred bytes of storage" is an answer.
Mistake #2: Calculating silently
Say the formula and assumptions out loud. An interviewer can help if they see your approach, and a small arithmetic slip matters much less than a clear method.
Mistake #3: Guessing instead of asking
Open questions are meant to be explored. Asking what the workload is shows the right way of thinking.
Practice Exercise
Challenge: A Mock Question
"Your core has a CPI of 1.5 on the target workload. A profile shows: base 1.0, branches 0.25, data cache misses 0.20, other 0.05. You have budget for one improvement. Option A halves branch mispredictions. Option B halves data cache misses, but adds one cycle of L1 hit latency, which costs 0.08 in load-use stalls." These numbers are assumptions for this exercise. Work out each option, and give your recommendation in three sentences.
Hint
Add up the stack for each option, and don't forget the extra cost of option B.
Solution
A: 1.0 + 0.125 + 0.20 + 0.05 = 1.375, a speedup of 1.09. B: 1.0 + 0.25 + 0.10 + 0.05 + 0.08 = 1.48, a speedup of 1.01. Recommendation: choose A, because it gains about 9 percent, while B's extra latency cancels nearly all its benefit. Before committing I would check the area and timing of the predictor, and confirm the profile on more workloads. If the memory penalty is likely to rise in future products, I would look for a way to keep B's capacity without adding hit latency.
Summary
- Give the idea, an example, and a cost, and state your formulas and assumptions out loud.
- Know the performance equation, Amdahl's law, CPI stacks and AMAT well enough to use them quickly.
- Be ready to split addresses and to walk through forwarding, branch prediction and cache states.
- Explain renaming, the reorder buffer, coherence and consistency in plain words.
- For open questions, start from the workload, and propose something simple with numbers.
