Design For Testability

Introduction to Design for Testability

Design for Testability (DFT) is a critical discipline in modern digital design that focuses on making integrated circuits easier to test after manufacturing. As chip complexity increases and transistor sizes shrink, manufacturing defects become more likely, making comprehensive testing essential. Without proper DFT techniques, testing a complex chip would be prohibitively expensive or even impossible.

The fundamental challenge in testing digital circuits is controllability and observability. Controllability refers to our ability to set internal circuit nodes to specific values, while observability refers to our ability to observe the values at internal nodes. In a typical design, most flip-flops and logic gates are buried deep inside the chip with limited access from external pins. DFT techniques solve this problem by adding special test circuitry that provides access to internal nodes during test mode.

Scan Chain Basics

What is a Scan Chain?

A scan chain is the cornerstone of modern DFT methodology. It transforms regular flip-flops in your design into scan flip-flops that can operate in two modes: normal mode and scan mode. In normal mode, the circuit operates as designed. In scan mode, all flip-flops are connected in a serial chain, allowing test patterns to be shifted in and results to be shifted out through a limited number of pins.

Scan Flip-Flop Architecture

A scan flip-flop includes additional multiplexing logic compared to a standard flip-flop:

Standard Flip-Flop:  D → [FF] → Q

Scan Flip-Flop:      D ----\
                            MUX → [FF] → Q
                     SI ---/
                           ↑
                          SE (Scan Enable)

The scan flip-flop has three key inputs:

• D: Normal data input used during functional mode
• SI: Scan input, connected to the previous flip-flop's output in the chain
• SE: Scan enable signal that selects between normal and scan mode

When SE=0 (normal mode), the flip-flop captures data from D, just like a regular flip-flop. When SE=1 (scan mode), the flip-flop captures data from SI, effectively making it part of a shift register.

How Scan Chains Work

During testing, the process follows these steps:

1. Scan-In Phase: Assert scan enable (SE=1) and shift test vectors through the scan chain, loading all flip-flops with predetermined values. This gives us controllability over internal state.

2. Capture Phase: Deassert scan enable (SE=0) for one or more clock cycles, allowing the circuit to operate normally with the loaded test pattern. The combinational logic processes the inputs, and flip-flops capture the results.

3. Scan-Out Phase: Assert scan enable (SE=1) again and shift out the captured values while simultaneously shifting in the next test pattern. This gives us observability of internal state.

This elegant approach allows us to test internal combinational logic by controlling flip-flop outputs (which serve as inputs to combinational blocks) and observing flip-flop inputs (which capture combinational block outputs).

Multiple Scan Chains

Large designs typically use multiple parallel scan chains rather than one long chain. This reduces test time since shorter chains require fewer clock cycles to load and unload. For example, a design with 10,000 flip-flops might use 10 chains of 1,000 flip-flops each, reducing scan shifting time by 10×.

The trade-off is that multiple chains require additional scan-in and scan-out pins, but this is usually worthwhile given the dramatic reduction in test time.

ATPG Concepts

What is ATPG?

Automatic Test Pattern Generation (ATPG) is the process of automatically creating test vectors that detect manufacturing defects. Manual test pattern creation is impractical for modern designs with millions of gates, so ATPG tools use sophisticated algorithms to generate high-quality test patterns efficiently.

Fault Models

ATPG tools target specific fault models that represent common manufacturing defects:

Stuck-At Faults: The most common fault model assumes that a signal line is permanently stuck at logic 0 (stuck-at-0) or logic 1 (stuck-at-1) due to manufacturing defects like opens or shorts. Even though real defects are more complex, the stuck-at fault model provides good coverage and is computationally tractable.

Transition Faults: These model timing-related defects where a signal fails to transition properly (slow-to-rise or slow-to-fall). Transition fault testing requires at-speed testing to detect these defects.

Bridging Faults: These model short circuits between two signal lines, which can cause unexpected logic behavior.

ATPG Algorithms

ATPG tools use various algorithms to generate test patterns:

Combinational ATPG: For testing combinational logic between flip-flops. The tool works backward from the fault site, determining what values are needed at flip-flop outputs to activate the fault, and forward from the fault site to propagate the fault effect to observable flip-flop inputs.

Sequential ATPG: More complex, as it must determine a sequence of patterns to reach and observe certain faults in circuits with feedback loops or sequential dependencies.

Fault Coverage

A critical metric is fault coverage, expressed as:

Fault Coverage = (Detected Faults / Total Faults) × 100%

Modern designs typically target 95-99% stuck-at fault coverage. Undetected faults fall into categories:

• Untestable faults: Logically impossible to test (e.g., floating inputs in scan mode)
• ATPG-resistant faults: Too computationally expensive to generate patterns for
• Acceptable faults: Deliberately excluded (e.g., faults in non-critical redundancy logic)

DFT Considerations in RTL

Design Rules for Testability

Writing DFT-friendly RTL requires following specific guidelines:

Avoid Combinational Loops: Combinational feedback loops make ATPG extremely difficult. Always break loops with flip-flops:

// Poor DFT - combinational loop
assign out = enable ? in : out;  // Latch behavior, hard to test

// Better DFT - explicit flip-flop
always @(posedge clk) begin
    if (enable)
        out <= in;
end

Avoid Gated Clocks: Clock gating for power savings can block scan chain operation. Instead, use enable signals on flip-flops:

// Problematic for DFT
wire gated_clk = clk & enable;
always @(posedge gated_clk) q <= d;

// DFT-friendly alternative
always @(posedge clk) begin
    if (enable)
        q <= d;
end

Modern synthesis tools can convert the second form into clock gating automatically while maintaining DFT compatibility.

Initialize All Flip-Flops: Provide proper reset mechanisms for all state elements. Uninitialized state makes test pattern generation difficult and results non-deterministic.

Avoid Asynchronous Logic: Asynchronous set/reset signals should be carefully controlled during scan operations. Prefer synchronous resets when possible:

// DFT-friendly synchronous reset
always @(posedge clk) begin
    if (reset)
        counter <= 0;
    else
        counter <= counter + 1;
end

Test Mode Considerations

Design your RTL with explicit test modes in mind:

module dft_friendly_module (
    input clk,
    input rst_n,
    input test_mode,      // Test mode signal
    input [7:0] data_in,
    output reg [7:0] data_out
);

    // In test mode, bypass complex logic
    wire [7:0] functional_result = complex_function(data_in);
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            data_out <= 8'b0;
        else if (test_mode)
            data_out <= data_in;  // Simple path for testing
        else
            data_out <= functional_result;
    end

endmodule

Memory and IP Considerations

Embedded Memories: RAMs and ROMs require special DFT techniques like Memory BIST (Built-In Self-Test) because they cannot be directly accessed through scan chains. Plan for BIST insertion during RTL design.

Third-Party IP: When integrating vendor IP blocks, understand their DFT features:

• Are scan chains provided or must they be added?
• What test modes are supported?
• Are there BIST capabilities for embedded memories?

Estimating DFT Impact

DFT insertion adds overhead:

• Area: Scan flip-flops are ~20-30% larger than regular flip-flops; scan routing adds more area
• Power: Scan shifting consumes significant power (often addressed with low-power scan techniques)
• Timing: Scan multiplexers may create critical paths; plan for this in your timing budgets

Estimate 5-15% area overhead for scan insertion in typical designs, though this varies with design characteristics and DFT requirements.

Conclusion

Design for Testability is not an afterthought but an integral part of modern digital design. By understanding scan chain principles, ATPG fundamentals, and following DFT-friendly RTL coding practices, you ensure your designs can be thoroughly tested after manufacturing. This reduces defect levels, improves yield, and ultimately delivers more reliable products to customers.

As you develop your RTL designs, always consider: "How will this be tested?" Making DFT-conscious decisions early in the design process is far easier and more effective than trying to retrofit testability into a completed design.

Key Takeaways:

• Scan chains provide controllability and observability for internal circuit nodes
• ATPG tools automatically generate test patterns targeting specific fault models
• DFT-friendly RTL coding practices are essential for achieving high fault coverage
• Plan for DFT early in the design process to minimize area, power, and schedule impact