Cell Characterization Data

The Bridge Between Silicon and Simulation

You've learned that Liberty files describe standard cells, and you understand why we need multiple process corners. Now it's time to dive into the actual electrical data that makes timing analysis possible: cell characterization data.

Think of cell characterization as the laboratory measurement process that translates physical silicon into numbers that EDA tools can use. Engineers fabricate test structures, apply thousands of different input conditions, measure the results with picosecond precision, and encode all that data into lookup tables. Every timing number in your static timing analysis report traces back to these measurements.

This module explores what gets measured, how it's represented in Liberty files, and why each piece of data matters for your design.

Understanding Timing Arcs

What Is a Timing Arc?

A timing arc represents the relationship between an input signal change and an output signal response. It's the fundamental building block of timing analysis.

Basic Definition
A timing arc specifies:

• Which input pin affects which output pin
• How the output responds (rising, falling, or both)
• The delay and transition time under various conditions

Arc Representation in Liberty

timing () {
    related_pin : "A";           // Input pin causing the change
    timing_sense : negative_unate;  // Output inverts input
    timing_type : combinational; // Type of arc
    
    /* Delay and transition tables follow */
}

Combinational Timing Arcs

Combinational logic has straightforward input-to-output timing relationships.

Inverter Example

cell (INV_X1) {
    pin (A) {
        direction : input;
        capacitance : 0.0015;
    }
    
    pin (Y) {
        direction : output;
        function : "!A";
        
        timing () {
            related_pin : "A";
            timing_sense : negative_unate;
            timing_type : combinational;
            
            /* When input A rises, output Y falls */
            cell_fall (delay_template_5x5) {
                index_1 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Input transition
                index_2 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Output load
                values ( \
                    "0.045, 0.053, 0.068, 0.098, 0.158", \
                    "0.048, 0.056, 0.071, 0.101, 0.161", \
                    "0.054, 0.062, 0.077, 0.107, 0.167", \
                    "0.066, 0.074, 0.089, 0.119, 0.179", \
                    "0.090, 0.098, 0.113, 0.143, 0.203" \
                );
            }
            
            /* When input A falls, output Y rises */
            cell_rise (delay_template_5x5) {
                index_1 ("0.01, 0.05, 0.1, 0.2, 0.4");
                index_2 ("0.01, 0.05, 0.1, 0.2, 0.4");
                values ( \
                    "0.052, 0.061, 0.078, 0.112, 0.180", \
                    "0.055, 0.064, 0.081, 0.115, 0.183", \
                    "0.061, 0.070, 0.087, 0.121, 0.189", \
                    "0.073, 0.082, 0.099, 0.133, 0.201", \
                    "0.097, 0.106, 0.123, 0.157, 0.225" \
                );
            }
            
            /* Output transition times also included */
            rise_transition (delay_template_5x5) { /* ... */ }
            fall_transition (delay_template_5x5) { /* ... */ }
        }
    }
}

Key Observations

• Separate tables for rising and falling outputs
• Delays increase with larger input transitions (slower input)
• Delays increase with larger output loads (more capacitance to drive)
• This is real measured data, not theoretical calculations

Multi-Input Gate Complexity

For a 2-input NAND gate, each input has its own timing arc:

cell (NAND2_X1) {
    pin (A) { direction : input; capacitance : 0.0018; }
    pin (B) { direction : input; capacitance : 0.0018; }
    
    pin (Y) {
        direction : output;
        function : "!(A & B)";
        
        /* Timing arc for A -> Y */
        timing () {
            related_pin : "A";
            timing_sense : negative_unate;
            when : "B";  // This arc is active when B is high
            /* Delay tables... */
        }
        
        /* Timing arc for B -> Y */
        timing () {
            related_pin : "B";
            timing_sense : negative_unate;
            when : "A";  // This arc is active when A is high
            /* Delay tables... */
        }
    }
}

Why Multiple Arcs Matter
The A→Y arc might have different delays than B→Y if the transistor stacks are asymmetric. The timing analyzer needs both arcs to accurately compute delays for all possible input transitions.

Timing Sense Classifications

The timing_sense attribute describes how the output relates to the input:

Positive Unate

• Output changes in the same direction as input
• Example: Buffer (input rises → output rises)
• Attribute: timing_sense : positive_unate;

Negative Unate

• Output changes in the opposite direction as input
• Example: Inverter (input rises → output falls)
• Attribute: timing_sense : negative_unate;

Non-Unate

• Output response depends on other input states
• Example: XOR gate (A→Y response depends on B's value)
• Attribute: timing_sense : non_unate;
• Requires more timing arcs to cover all cases

Sequential Cell Timing

Sequential elements (flip-flops and latches) have significantly more complex timing requirements than combinational gates.

Setup Time: The "Data Must Arrive Early" Constraint

Physical Explanation
Before a flip-flop can reliably capture data on a clock edge, the data must be stable for a minimum time called the setup time. This allows the internal master latch to fully resolve the data state.

Setup Time Definition
The minimum time data must be stable BEFORE the active clock edge.

Liberty Representation

ff ("IQ", "IQN") {
    next_state : "D";
    clocked_on : "CP";  // Clock pin
    
    /* Setup constraint for D with respect to CP */
    timing () {
        related_pin : "D";
        timing_type : setup_rising;  // Setup for rising clock edge
        
        rise_constraint (setup_template_5x5) {
            index_1 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Data transition
            index_2 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Clock transition
            values ( \
                "0.085, 0.090, 0.098, 0.114, 0.146", \
                "0.083, 0.088, 0.096, 0.112, 0.144", \
                "0.079, 0.084, 0.092, 0.108, 0.140", \
                "0.071, 0.076, 0.084, 0.100, 0.132", \
                "0.055, 0.060, 0.068, 0.084, 0.116" \
            );
        }
        
        fall_constraint (setup_template_5x5) {
            /* Setup time for falling data edge */
        }
    }
}

Reading the Table

• Row index: Data transition time (how fast data changes)
• Column index: Clock transition time (how fast clock edge rises)
• Values: Required setup time in nanoseconds

Key Insight
Faster input transitions (smaller index values) generally require MORE setup time because the flip-flop's internal nodes switch more rapidly and need more time to settle.

Hold Time: The "Data Must Stay Stable" Constraint

Physical Explanation
After the clock edge captures data, the data must remain stable for a minimum time called the hold time. This ensures the internal master latch has completely captured the data before it can change.

Hold Time Definition
The minimum time data must remain stable AFTER the active clock edge.

Liberty Representation

/* Hold constraint for D with respect to CP */
timing () {
    related_pin : "D";
    timing_type : hold_rising;  // Hold for rising clock edge
    
    rise_constraint (hold_template_5x5) {
        index_1 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Data transition
        index_2 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Clock transition
        values ( \
            "0.042, 0.038, 0.031, 0.017, -0.015", \
            "0.044, 0.040, 0.033, 0.019, -0.013", \
            "0.048, 0.044, 0.037, 0.023, -0.009", \
            "0.056, 0.052, 0.045, 0.031, -0.001", \
            "0.072, 0.068, 0.061, 0.047, 0.015" \
        );
    }
    
    fall_constraint (hold_template_5x5) {
        /* Hold time for falling data edge */
    }
}

Negative Hold Times?
Notice some values are negative. This means data can change slightly before the clock edge and still be captured correctly. This happens in well-designed flip-flops where the master latch closes very quickly.

Critical Design Implication
Hold violations are catastrophic:

• Cannot be fixed by slowing down the clock
• Require physical changes (adding delay buffers)
• Must be verified at FF (fast-fast) corner where delays are minimum

Clock-to-Q Delay: The "Output Response Time"

Physical Explanation
After the clock edge triggers the flip-flop, there's a delay before the output Q reflects the captured data. This delay depends on the flip-flop's internal propagation and the load it's driving.

Liberty Representation

/* Clock-to-output timing arc */
timing () {
    related_pin : "CP";
    timing_type : rising_edge;  // Triggered by rising clock
    timing_sense : non_unate;   // Output depends on data, not clock direction
    
    cell_rise (delay_template_5x5) {
        index_1 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Clock transition
        index_2 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Output load
        values ( \
            "0.156, 0.168, 0.192, 0.240, 0.336", \
            "0.160, 0.172, 0.196, 0.244, 0.340", \
            "0.168, 0.180, 0.204, 0.252, 0.348", \
            "0.184, 0.196, 0.220, 0.268, 0.364", \
            "0.216, 0.228, 0.252, 0.300, 0.396" \
        );
    }
    
    cell_fall (delay_template_5x5) {
        /* Clock-to-Q delay for falling output */
    }
    
    rise_transition (delay_template_5x5) {
        /* Output transition time for rising edge */
    }
    
    fall_transition (delay_template_5x5) {
        /* Output transition time for falling edge */
    }
}

The Complete Timing Picture

For a path from one flip-flop to another:

Launch Flop   Combinational   Capture Flop
    CP        →    Logic    →      CP
    |              |               |
    |--Tclk2q------|               |
                   |----Tlogic-----|
                                   |--Tsetup--
    
Total path delay = Tclk2q + Tlogic
Clock period must be ≥ Tclk2q + Tlogic + Tsetup

This is the fundamental setup timing equation that drives all digital design.

Propagation Delays in Detail

The Two-Dimensional Lookup Model

Every combinational cell delay is characterized as a 2D function:

Delay = f(input_transition, output_load)

Why These Two Variables?

Input Transition Time
Slower input transitions mean:

• Input spends more time in the linear region
• Internal nodes take longer to switch
• Overall delay increases

Fast input (0.01ns) vs. slow input (0.4ns) might show 2-3× delay difference.

Output Load Capacitance
Larger loads mean:

• More charge must be transferred
• Output voltage changes more slowly
• Overall delay increases

Light load (0.01pF) vs. heavy load (0.4pF) might show 3-5× delay difference.

Non-Linear Behavior
These relationships are NOT linear:

• Doubling load doesn't double delay
• The delay surface is curved, not flat
• This is why we need lookup tables, not simple equations

Cell Rise vs. Cell Fall

Most cells have asymmetric behavior:

NMOS vs. PMOS Strength

• NMOS transistors (pull-down) are naturally stronger
• PMOS transistors (pull-up) are naturally weaker (≈2-3× larger for same drive)
• This creates different rise and fall delays

Example: Inverter Delays

Input rising → Output falling: 45ps (fast, NMOS pulling down)
Input falling → Output rising: 52ps (slow, PMOS pulling up)

Design Impact
Clock trees must account for this asymmetry:

• Different delays for positive vs. negative edge paths
• Duty cycle distortion accumulates through many stages
• May require duty cycle correction circuits

Transition Times (Slew Rates)

What Is Transition Time?

Transition time (also called slew or slew rate) measures how fast a signal changes between logic levels.

Standard Definition
Time for the signal to transition between 20% and 80% of the supply voltage range.

• For 1.8V supply: transition from 0.36V to 1.44V
• Some libraries use 10%-90% or 30%-70%

Why It Matters

Downstream Delay Calculation
The output transition time of one gate becomes the input transition time for the next gate:

Gate A output transition → Gate B input transition → Gate B delay calculation

If you ignore transition time propagation, your timing analysis is wrong.

Signal Integrity
Very slow transitions (large slew):

• Increased susceptibility to noise
• More time spent in the undefined region between logic 0 and 1
• Can cause multiple switching events in downstream gates

Very fast transitions (small slew):

• Ground bounce and power supply noise
• Electromagnetic interference (EMI)
• Signal integrity issues on long wires

Transition Time Tables

Liberty Representation

rise_transition (delay_template_5x5) {
    index_1 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Input transition
    index_2 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Output load
    values ( \
        "0.025, 0.034, 0.052, 0.088, 0.160", \
        "0.027, 0.036, 0.054, 0.090, 0.162", \
        "0.031, 0.040, 0.058, 0.094, 0.166", \
        "0.039, 0.048, 0.066, 0.102, 0.174", \
        "0.055, 0.064, 0.082, 0.118, 0.190" \
    );
}

Reading the Data

• Diagonal terms (0.025, 0.036, 0.058, 0.102, 0.190) show that matching input/output conditions produce varied transitions
• Larger loads produce slower transitions
• Slower input transitions tend to produce slower output transitions

Design Constraints
Most libraries specify maximum transition time limits:

max_transition : 0.5;  // nanoseconds

If your design exceeds this limit:

• Characterization data becomes invalid (extrapolation is unreliable)
• You need to upsize the driving cell or add buffers

Capacitance Values

Input Capacitance

Physical Source
Input capacitance comes from:

• Gate oxide capacitance of input transistors
• Diffusion capacitance of internal nodes
• Interconnect capacitance within the cell

Liberty Representation

pin (A) {
    direction : input;
    capacitance : 0.0018;  // In library capacitance units (pF)
    
    /* May also specify rise/fall separately */
    rise_capacitance : 0.0019;
    fall_capacitance : 0.0017;
}

Why It Varies

• Larger drive strength cells have larger input transistors → more capacitance
• INV_X1: 0.0015 pF
• INV_X2: 0.0030 pF (2× the transistor width)
• INV_X4: 0.0060 pF (4× the transistor width)

Design Impact
Input capacitance of the load directly affects the driving cell's delay:

Driver output load = Wire capacitance + Sum of all input capacitances

Output Capacitance and Pin Capacitance

Output Pin Capacitance
The intrinsic capacitance of the output pin itself:

pin (Y) {
    direction : output;
    capacitance : 0.0008;  // Much smaller than input cap
}

This is the parasitic capacitance even with no external load.

Max Capacitance Constraint
Cells have maximum load limits:

pin (Y) {
    direction : output;
    max_capacitance : 0.5;  // Maximum safe load
}

Exceeding this limit:

• Invalidates the characterization data
• May cause functional failures (output doesn't reach valid logic levels)
• Requires buffer insertion

Capacitance in Timing Calculation

Complete Load Calculation

Total_output_load = Output_pin_cap 
                  + Wire_capacitance 
                  + Sum(Input_capacitances_of_fanout_cells)

Example Calculation

Driver: INV_X2
  Output pin capacitance: 0.0008 pF
  
Wire: 500μm metal-2
  Parasitic capacitance: 0.020 pF
  
Loads: 4× INV_X1 inputs
  Each input: 0.0015 pF
  Total: 4 × 0.0015 = 0.006 pF

Total load = 0.0008 + 0.020 + 0.006 = 0.0268 pF

This total load is used to index into the delay tables.

Practical Application Example

Let's trace through a complete timing calculation:

Circuit Path

FF1/Q → INV1/A → INV1/Y → NAND2/A → NAND2/Y → FF2/D

Step 1: Clock-to-Q Delay (FF1)

• Clock transition: 0.05ns
• Output load (to INV1): 0.025pF
• Look up in FF1 clock-to-Q table: 0.168ns
• Output transition: 0.040ns (from transition table)

Step 2: Inverter Delay (INV1)

• Input transition: 0.040ns (from FF1 output)
• Output load (to NAND2): 0.030pF
• Look up in INV1 delay table: 0.058ns
• Output transition: 0.045ns

Step 3: NAND Gate Delay (NAND2)

• Input transition: 0.045ns
• Output load (to FF2): 0.020pF
• Look up in NAND2 delay table: 0.063ns
• Output transition: 0.038ns

Step 4: Setup Time Check (FF2)

• Data transition: 0.038ns
• Clock transition: 0.05ns
• Look up in FF2 setup table: 0.090ns

Total Path Delay

Tclk2q + Tinv + Tnand = 0.168 + 0.058 + 0.063 = 0.289ns

Required Clock Period

Tperiod ≥ Tpath + Tsetup = 0.289 + 0.090 = 0.379ns
Maximum frequency ≈ 2.64 GHz

This is exactly how timing analyzers work—millions of these calculations for every path in your design.

Common Characterization Pitfalls

Pitfall 1: Extrapolation Beyond Table Range
Problem: Your design has a 0.8ns input transition, but the table only goes to 0.4ns
Impact: Tool extrapolates linearly (wrong! nonlinear behavior)
Solution: Upsize drivers or insert buffers to keep transitions within characterized range

Pitfall 2: Ignoring Transition Times
Problem: Only looking at delays, not checking transition constraints
Impact: Invalid timing analysis, potential functional failures
Solution: Always verify max_transition constraints are met

Pitfall 3: Misunderstanding Setup/Hold
Problem: Confusing which corner to use (SS for setup, FF for hold)
Impact: Missing timing violations in actual silicon
Solution: Remember—setup needs maximum delays (SS), hold needs minimum delays (FF)

Pitfall 4: Wrong Capacitance Units
Problem: Liberty uses pF, parasitic extraction uses fF
Impact: 1000× error in load calculation
Solution: Always check and convert units carefully

Integration with Design Flow

During Synthesis

• Tool selects cells based on area, delay, and power from Liberty data
• Input capacitances affect fanout decisions
• Max capacitance constraints limit fanout

During Place and Route

• Physical locations determine wire capacitances
• Actual loads computed from wire caps + input caps
• Timing recalculated with accurate load values

During Sign-Off STA

• Full multi-corner analysis using complete Liberty suites
• Both rise and fall paths checked
• Setup at SS corner, hold at FF corner
• All transition time constraints verified

Summary

Cell characterization data is the foundation of timing analysis:

• Timing arcs define input-to-output relationships for combinational and sequential cells
• Setup time specifies minimum data stability before clock edge
• Hold time specifies minimum data stability after clock edge
• Clock-to-Q delay defines sequential cell output response time
• Propagation delays are 2D functions of input transition and output load
• Transition times propagate through the design and affect downstream delays
• Capacitance values determine loading effects and drive requirements

Every number in your timing reports comes from this characterized data. Understanding how cells are measured, how data is represented, and how tools use this information is essential for effective timing closure. The Liberty file transforms silicon physics into numbers that computers can work with—and understanding this transformation makes you a more effective digital designer.

In the next module, we'll explore the mathematical models behind these lookup tables and dive into advanced characterization topics like composite current source models and statistical timing.