Introduction to Low Power Design
Power consumption has become one of the most critical design constraints in modern digital systems. From mobile devices fighting for battery life to data centers consuming megawatts of electricity, power directly impacts product success, operating costs, and environmental sustainability. While early digital designs focused primarily on performance and area, today's designs must carefully balance the "PPA triad": Performance, Power, and Area.
Digital circuits consume power through two primary mechanisms:
Dynamic Power: Power consumed during signal transitions
P_dynamic = α × C × V² × f
Where:
- α = activity factor (fraction of time signal toggles)
- C = capacitance being switched
- V = supply voltage
- f = clock frequency
Static Power (Leakage): Power consumed even when circuits are idle
P_static = V × I_leakage
Where leakage current increases with temperature and smaller process nodes
In modern designs (especially below 28nm), static power can equal or exceed dynamic power, making both crucial optimization targets. This module explores four key techniques for reducing power consumption while maintaining functionality.
Clock Gating: The Foundation of Low Power Design
Understanding Clock Power Consumption
The clock network is often the largest consumer of dynamic power in a design, typically accounting for 30-50% of total chip power. This happens because:
- Clock signals toggle every cycle (α = 1.0 vs. 0.1-0.2 for data signals)
- Clock trees drive huge capacitance (millions of flip-flops)
- Clock buffers are large to meet timing requirements
What is Clock Gating?
Clock gating disables the clock to portions of the design when those blocks aren't performing useful work, eliminating unnecessary switching activity:
// Without clock gating - always clocking
always @(posedge clk) begin
if (enable)
register <= new_data;
else
register <= register; // Wasteful: clocking to keep same value
end
The problem: Even when enable is low, the flip-flop still consumes power from clock switching and internal transitions.
Integrated Clock Gating (ICG) Cells
Modern designs use Integrated Clock Gating (ICG) cells—special library cells that safely gate clocks:
// RTL style that inference tools convert to ICG
always @(posedge clk) begin
if (enable)
register <= new_data;
end
// Synthesis converts to:
// [clk] ──→ [ICG Cell] ──gated_clk──→ [FF]
// ↑
// [enable]
ICG Cell Architecture
A proper ICG cell includes:
┌──────────────┐
clk ────┤ │
│ Latch │ AND gated_clk
enable ──┤ (avoid ├────(or)────→
│ glitches) │ OR
└──────────────┘
Key components:
- Enable Latch: Triggered on clock's inactive edge to prevent glitches
- AND/OR Gate: Combines latched enable with clock
- Glitch-Free Operation: Enable changes only when clock is stable
Latch-Based ICG Implementation
module icg_cell (
input wire clk,
input wire enable,
input wire test_enable, // For DFT
output wire gated_clk
);
reg enable_latched;
// Latch opens on clock low (for AND-based gating)
always @(*) begin
if (!clk)
enable_latched = enable | test_enable;
end
// Generate gated clock
assign gated_clk = clk & enable_latched;
endmodule
Critical: The latch captures enable when clk is low. When clk goes high, enable_latched is stable, preventing glitches on gated_clk.
Clock Gating Guidelines
Guideline 1: Let Synthesis Tools Insert ICG Cells
Write simple enable-based code; let tools handle ICG insertion:
// Good: Clear enable condition
always @(posedge clk) begin
if (state_machine_active)
result <= compute(input_data);
end
// Tools automatically insert: clk → ICG → gated_clk → result_reg
Guideline 2: Group Registers for Efficiency
ICG cells have area/power overhead. Only gate groups of registers (typically ≥4):
// Efficient: One ICG for 32-bit register
always @(posedge clk) begin
if (update_enable)
data_reg[31:0] <= new_data[31:0];
end
// Inefficient: 32 separate ICGs (if enable differs per bit)
generate
for (i = 0; i < 32; i++) begin
always @(posedge clk) begin
if (enable[i])
data_reg[i] <= new_data[i];
end
end
endgenerate
Guideline 3: Verify DFT Compatibility
ICG cells must include test enable signals to allow scan chain operation:
module design_top (
input clk,
input test_mode, // From DFT controller
// ... other ports
);
wire gated_clk;
icg_cell u_icg (
.clk(clk),
.enable(functional_enable),
.test_enable(test_mode), // Disables gating in test mode
.gated_clk(gated_clk)
);
endmodule
Clock Gating Benefits
Properly applied clock gating typically saves:
- 20-40% dynamic power in control logic
- 10-25% total chip power in typical applications
- 50%+ power in blocks with low activity factors
Power Gating: Shutting Down Unused Blocks
What is Power Gating?
Power gating completely removes power from inactive circuit blocks, eliminating both dynamic and static power:
Normal Operation:
VDD ───────────────→ [Circuit Block]
GND ───────────────→
Power Gated:
VDD ──┤│──[Header SW]───→ [Circuit Block]
OPEN (No power = No leakage!)
Power Switch Implementation
Power switches use large PMOS (header) or NMOS (footer) transistors:
// Conceptual power domain
module power_domain (
input power_enable,
input vdd,
input gnd,
// ... functional signals
);
// Header switch (PMOS): connects VDD when enabled
wire virtual_vdd;
// In actual implementation, this is a special cell
power_switch_cell u_pwr_sw (
.vdd_in(vdd),
.vdd_out(virtual_vdd),
.enable(power_enable)
);
// All circuitry in domain uses virtual_vdd
// ... functional logic here
endmodule
State Retention
When powering down, register state is lost. Solutions include:
1. Retention Flops: Special flip-flops with battery/always-on power:
// Standard FF: loses state when powered down
always @(posedge clk) state <= next_state;
// Retention FF: keeps state in special latch
(* retention_purpose = "save" *)
reg [7:0] critical_state;
always @(posedge clk) begin
if (save_enable)
critical_state <= current_state;
end
2. Memory Shadowing: Save state to always-on memory before power-down:
// Before entering power-down
always @(posedge clk) begin
if (entering_sleep_mode) begin
backup_memory[addr] <= critical_registers;
power_gate_enable <= 1'b1;
end
end
// After power-up
always @(posedge clk) begin
if (exiting_sleep_mode) begin
critical_registers <= backup_memory[addr];
end
end
Power Gating Challenges
Inrush Current: Turning on all switches simultaneously causes huge current spike:
Solution: Gradual power-up sequence
Time: t0 t1 t2 t3
Switch: 25% → 50% → 75% → 100% (staged activation)
Wake-up Latency: Power-gating transitions take microseconds to milliseconds—too slow for fine-grained control. Use for coarse-grained blocks (entire subsystems).
Isolation Cells: Powered-off blocks can output undefined values. Insert isolation cells at domain boundaries:
module isolation_cell (
input data_in,
input iso_enable, // From power controller
output data_out
);
// When isolated, force known value
assign data_out = iso_enable ? 1'b0 : data_in;
endmodule
Multi-Threshold Voltage (Multi-Vt) Cells
Understanding Threshold Voltage
Threshold voltage (Vt) is the gate voltage needed to turn on a transistor. This parameter profoundly affects both performance and leakage:
Low-Vt: Fast switching, HIGH leakage ⚡ 💧💧💧
Mid-Vt: Balanced performance/leakage ⚖️ 💧💧
High-Vt: Slow switching, LOW leakage 🐌 💧
Why Multi-Vt Matters
At advanced nodes (28nm and below), leakage power dominates. Multi-Vt libraries provide cells with different Vt options for the same logic function, enabling designers to trade off speed vs. leakage.
Multi-Vt Cell Selection Strategy
Synthesis tools select cell Vt based on timing criticality:
Critical Path: A → B → C → D
↓ ↓ ↓ ↓
LVT LVT LVT LVT (Fast, but leaky)
Non-Critical: E → F → G
↓ ↓ ↓
HVT HVT HVT (Slow, but low leakage)
Optimization Process:
- Initial Synthesis: All standard-Vt cells
- Timing Analysis: Identify critical paths
- LVT Assignment: Use LVT on critical paths to meet timing
- HVT Assignment: Use HVT on non-critical paths (have timing slack)
- Iteration: Balance until timing met with minimum leakage
Multi-Vt in RTL (Directives)
While tools auto-select Vt, designers can guide the process:
// Hint: This path is timing-critical
(* use_low_vt = "true" *)
module high_speed_datapath (
input clk,
input [31:0] data_in,
output [31:0] data_out
);
// Critical arithmetic operations
endmodule
// Hint: This is non-critical control logic
(* use_high_vt = "true" *)
module control_unit (
input clk,
input start,
output reg done
);
// State machine with loose timing
endmodule
Multi-Vt Results
Typical multi-Vt optimization achieves:
- 20-40% leakage reduction
- 0-5% timing degradation (if done correctly)
- Minimal area impact (same footprint cells)
Power Analysis in Liberty Files
Liberty File Structure
.lib files (Liberty format) contain timing, power, and functional information for standard cells:
library (my_library_typ) {
voltage_unit : "1V";
current_unit : "1mA";
leakage_power_unit : "1nW";
cell (AND2_X1) {
area : 2.5;
leakage_power () {
value : 0.025; /* 25 pW static leakage */
}
pin (A) {
direction : input;
capacitance : 0.5; /* Input cap in fF */
}
pin (Y) {
direction : output;
function : "(A & B)";
internal_power () {
related_pin : "A";
rise_power (power_template) {
values ("0.15, 0.18, 0.22"); /* Energy per transition */
}
fall_power (power_template) {
values ("0.12, 0.14, 0.17");
}
}
}
}
}
Key Power Parameters
1. Leakage Power: Static power consumption when idle
leakage_power () {
when : "A & !B"; /* State-dependent leakage */
value : 0.030; /* Higher leakage in this state */
}
leakage_power () {
when : "!A & B";
value : 0.020; /* Lower leakage here */
}
2. Internal Power: Energy consumed by cell switching
internal_power () {
related_pin : "CLK";
rise_power (scalar) {
values ("0.50"); /* Energy when CLK rises */
}
}
3. Switching Power: Energy to charge output capacitance (calculated by tools)
Switching Power = C_load × V² × f × α
Where C_load from pin capacitances in Liberty file
Power Analysis Flow
Step 1: Activity Annotation
Tools need signal activity (toggle rates):
# From simulation VCD file
read_vcd simulation.vcd -strip_path testbench/dut
# From static probability (less accurate)
set_switching_activity -period 10 -toggle_rate 0.1 [get_nets data_bus*]
Step 2: Power Calculation
# Run power analysis
report_power -hierarchy -verbose
# Output example:
# Instance Dynamic Leakage Total
# ----------- ------- ------- -----
# datapath 45.2 mW 12.3 mW 57.5 mW
# control 5.8 mW 2.1 mW 7.9 mW
# clock_tree 30.5 mW 0.5 mW 31.0 mW
# ----------- ------- ------- -----
# Total 81.5 mW 14.9 mW 96.4 mW
Step 3: Optimization
Based on report, apply techniques:
- Clock gating for high-activity, low-utilization blocks
- Multi-Vt for blocks with timing slack
- Power gating for rarely used subsystems
Multi-Corner Power Analysis
Power varies with PVT (Process, Voltage, Temperature):
# Worst leakage: Fast process, high voltage, high temp
set_operating_conditions -library fast_1.2V_125C
# Best leakage: Slow process, low voltage, low temp
set_operating_conditions -library slow_0.8V_-40C
report_power -scenario worst_leakage
report_power -scenario best_leakage
Design must meet power budgets across all corners.
Integrated Low Power Flow
Modern low-power design integrates all techniques:
1. RTL Design
↓ (Code with enable conditions for clock gating)
2. Synthesis
↓ (Insert ICG cells, select multi-Vt)
3. Power Analysis
↓ (Identify high-power blocks)
4. Optimization
↓ (More clock gating, Vt tuning)
5. Power Domain Definition
↓ (UPF: Unified Power Format)
6. Implementation
↓ (Insert power switches, isolation, level shifters)
7. Verification
↓ (Power-aware simulation, formal checks)
8. Sign-off
└→ (Multi-corner power analysis, IR drop)
UPF Example (Unified Power Format)
# Define power domains
create_power_domain PD_CORE
create_power_domain PD_PERIPHERAL -elements {peripheral_block}
# Supply network
create_supply_port VDD
create_supply_net VDD_CORE -domain PD_CORE
create_supply_net VDD_PERIPH -domain PD_PERIPHERAL
# Power states
add_power_state PD_PERIPHERAL \
-state ACTIVE {-supply_expr {VDD_PERIPH == 1.0}} \
-state OFF {-supply_expr {VDD_PERIPH == 0.0}}
# Isolation strategy
set_isolation iso_periph -domain PD_PERIPHERAL \
-isolation_signal iso_enable \
-clamp_value 0
Conclusion
Low power design requires a comprehensive approach spanning multiple abstraction levels and employing complementary techniques:
- Clock gating reduces dynamic power in active logic (20-40% savings)
- Power gating eliminates static power in inactive blocks (near 100% savings when off)
- Multi-Vt cells optimize the performance/leakage tradeoff (20-40% leakage reduction)
- Liberty files provide the foundational data enabling accurate power analysis
Success requires understanding the interplay between these techniques and the tools that apply them. Start with RTL that enables clock gating, use synthesis tools to optimize Vt assignment, and employ power gating for coarse-grained power management. Always validate with comprehensive power analysis across all operating conditions.
The investment in low-power techniques pays immediate dividends in battery life, thermal management, and operating costs while becoming increasingly critical as process geometries shrink and leakage currents rise.
Key Takeaways:
- Dynamic power (α × C × V² × f) and static power (V × I_leakage) both matter
- Clock gating is the most effective technique for dynamic power reduction
- Power gating eliminates both dynamic and static power but has state retention challenges
- Multi-Vt optimization balances speed and leakage on a cell-by-cell basis
- Liberty files encode the power characteristics that enable accurate analysis
