The Magic Translation: From Design Intent to Silicon
You've written your RTL code, simulated it, verified its functionality, and understood the technology library through Liberty files. Now comes one of the most critical steps in digital design: logic synthesis. This is where your abstract hardware description transforms into a concrete netlist of gates that can actually be fabricated.
Logic synthesis is often called the "compiler" of hardware design, but it's far more sophisticated than any software compiler. While a C compiler translates code into assembly instructions, a synthesis tool must navigate a vast solution space, making millions of optimization decisions to balance competing goals: speed, area, and power. Understanding synthesis fundamentals is essential for writing synthesizable RTL and achieving successful designs.
What Is Logic Synthesis?
The Core Definition
Logic synthesis is the automated process of converting a high-level hardware description (RTL) into an optimized gate-level netlist composed of standard cells from a technology library.
Input: RTL code (Verilog, VHDL, SystemVerilog)
module adder (
input [7:0] a,
input [7:0] b,
output [8:0] sum
);
assign sum = a + b;
endmodule
Output: Gate-level netlist
module adder (
input [7:0] a,
input [7:0] b,
output [8:0] sum
);
wire [7:0] carry;
XOR2_X1 xor_0 (.A(a[0]), .B(b[0]), .Y(sum[0]));
AND2_X1 and_0 (.A(a[0]), .B(b[0]), .Y(carry[0]));
// Full adders for remaining bits
FA_X1 fa_1 (.A(a[1]), .B(b[1]), .CI(carry[0]), .S(sum[1]), .CO(carry[1]));
FA_X1 fa_2 (.A(a[2]), .B(b[2]), .CI(carry[1]), .S(sum[2]), .CO(carry[2]));
// ... more instances ...
endmodule
Why Synthesis Is Necessary
Abstraction Management
RTL operates at a register-transfer level, describing data movement and transformations. Physical silicon operates at the transistor level. Synthesis bridges this 1000× complexity gap.
Optimization
Manual gate-level design for modern chips (millions of gates) is impossible. Synthesis tools explore billions of potential implementations to find efficient solutions.
Technology Independence
Well-written RTL can be synthesized for different technology libraries (TSMC 28nm, Samsung 14nm, etc.) without code changes. The synthesis tool handles technology-specific optimization.
Design Productivity
Writing RTL is 10-100× faster than manual gate-level design, enabling modern system-on-chip complexity.
What Synthesis Is NOT
Not Simulation
Synthesis doesn't verify functionality—it assumes your RTL is correct. Always simulate before and after synthesis.
Not Magic
Bad RTL produces bad results. Synthesis can't fix fundamental algorithmic or architectural problems.
Not Guaranteed to Close Timing
Synthesis provides an initial implementation. Timing closure often requires iterations with place-and-route.
Not Complete Physical Design
Synthesis produces a logical netlist. Placement, routing, and physical verification come later.
The RTL to Netlist Transformation
The Multi-Stage Synthesis Flow
Modern synthesis follows a well-defined sequence:
1. RTL Analysis (Parsing and Elaboration)
Input: RTL files
Process: Parse syntax, elaborate hierarchy, check semantics
Output: Internal representation (IR) of design
The tool builds an abstract syntax tree (AST) and resolves parameters, generates instances, and checks for syntax errors.
2. Generic Logic Optimization (Technology-Independent)
Input: Internal representation
Process: Boolean optimization, constant propagation, dead code elimination
Output: Optimized generic logic
At this stage, the design uses generic gates (AND, OR, NOT, flip-flops) without any technology mapping.
3. Technology Mapping (Technology-Dependent)
Input: Optimized generic logic + Technology library
Process: Map generic gates to actual standard cells
Output: Technology-mapped netlist
This is where Liberty files become crucial—the tool selects actual cells (NAND2_X1, INV_X2, etc.) from your library.
4. Logic Optimization (Technology-Specific)
Input: Mapped netlist
Process: Restructuring, resizing, buffering
Output: Optimized gate-level netlist
Post-mapping optimization refines the implementation using technology-specific information.
5. Netlist Generation
Input: Optimized netlist
Process: Format conversion
Output: Gate-level Verilog, EDIF, or other formats
Synthesis Abstraction Levels
RTL Level (Input)
// High-level description
always @(posedge clk) begin
if (enable)
counter <= counter + 1;
end
Boolean Level (Intermediate)
// Generic logic equations
next_counter[0] = counter[0] XOR enable
next_counter[1] = counter[1] XOR (counter[0] AND enable)
// Flip-flops to hold state
Gate Level (Output)
// Actual standard cells
XOR2_X1 xor_0 (.A(counter[0]), .B(enable), .Y(n1));
AND2_X1 and_0 (.A(counter[0]), .B(enable), .Y(n2));
XOR2_X1 xor_1 (.A(counter[1]), .B(n2), .Y(n3));
DFF_X1 ff_0 (.D(n1), .CK(clk), .Q(counter[0]));
DFF_X1 ff_1 (.D(n3), .CK(clk), .Q(counter[1]));
Example: Multiplexer Transformation
Let's trace a 4-to-1 multiplexer through synthesis:
RTL Code
module mux4to1 (
input [1:0] sel,
input [3:0] data,
output reg out
);
always @(*) begin
case (sel)
2'b00: out = data[0];
2'b01: out = data[1];
2'b10: out = data[2];
2'b11: out = data[3];
endcase
end
endmodule
Boolean Representation
out = (!sel[1] & !sel[0] & data[0]) |
(!sel[1] & sel[0] & data[1]) |
( sel[1] & !sel[0] & data[2]) |
( sel[1] & sel[0] & data[3])
Technology Mapping Options
Option 1: AND-OR structure
AND3_X1 a0 (.A(!sel[1]), .B(!sel[0]), .C(data[0]), .Y(p0));
AND3_X1 a1 (.A(!sel[1]), .B(sel[0]), .C(data[1]), .Y(p1));
AND3_X1 a2 (.A(sel[1]), .B(!sel[0]), .C(data[2]), .Y(p2));
AND3_X1 a3 (.A(sel[1]), .B(sel[0]), .C(data[3]), .Y(p3));
OR4_X1 or_final (.A(p0), .B(p1), .C(p2), .D(p3), .Y(out));
Option 2: Tree of 2-to-1 muxes
MUX2_X1 m0 (.A(data[0]), .B(data[1]), .S(sel[0]), .Y(w0));
MUX2_X1 m1 (.A(data[2]), .B(data[3]), .S(sel[0]), .Y(w1));
MUX2_X1 m2 (.A(w0), .B(w1), .S(sel[1]), .Y(out));
Option 3: Using AOI (AND-OR-INVERT) gates
AOI22_X1 aoi0 (.A(p0), .B(p1), .C(p2), .D(p3), .Y(!out));
INV_X1 inv_out (.A(!out), .Y(out));
The Synthesis Decision
The tool evaluates each option using Liberty file data:
- Area: Count of cells and their sizes
- Timing: Propagation delays through each path
- Power: Switching activity and cell power
It then selects the best option based on optimization constraints.
Technology Mapping Concepts
What Is Technology Mapping?
Technology mapping is the process of implementing Boolean logic functions using the specific gates available in your technology library.
The Challenge
Given:
- A Boolean function:
F = A & B | C & D - A library with: {INV, NAND2, NOR2, AOI22, MUX2}
Find the best implementation considering area, delay, and power.
Pattern Matching and Covering
Pattern Matching
The synthesis tool identifies patterns in your logic that match cells in the library:
Pattern: Y = !(A & B)
Matches: NAND2_X1 cell
Pattern: Y = !(A | B)
Matches: NOR2_X1 cell
Pattern: Y = !((A & B) | (C & D))
Matches: AOI22_X1 cell (AND-OR-INVERT)
The Covering Problem
Given a logic network, find the minimum-cost set of library cells that implements it:
Original logic:
F = (A & B) | (C & D)
Covering 1: (2 AND gates + 1 OR gate)
n1 = A & B [AND2_X1]
n2 = C & D [AND2_X1]
F = n1 | n2 [OR2_X1]
Total: 3 cells
Covering 2: (1 complex gate)
F = (A & B) | (C & D) [OAI22_X1 + INV_X1]
Total: 2 cells
Covering 3: (4 NAND gates - De Morgan's laws)
n1 = !(A & B) [NAND2_X1]
n2 = !(C & D) [NAND2_X1]
F = !(n1 & n2) [NAND2_X1]
Total: 3 NAND gates
The tool uses algorithms to find the optimal covering.
Drive Strength Selection
Most libraries offer multiple drive strengths for the same logic function:
INV_X1: Area=1.0, Delay=100ps, Input_cap=1fF
INV_X2: Area=1.5, Delay=60ps, Input_cap=2fF
INV_X4: Area=2.5, Delay=40ps, Input_cap=4fF
INV_X8: Area=4.5, Delay=30ps, Input_cap=8fF
Selection Criteria
- Light load, no timing pressure: Use X1 (smallest area)
- Heavy load, timing critical: Use X4 or X8 (faster)
- Medium load, some slack: Use X2 (balance)
The tool makes these decisions using Liberty file timing and capacitance data.
Mapping for Combinational Logic
Simple Gate Mapping
// RTL
assign y = a & b;
// Mapped
AND2_X1 u1 (.A(a), .B(b), .Y(y));
Complex Expression Mapping
// RTL
assign result = (a & b) | (c & !d);
// Mapped (using AOI gate)
INV_X1 u1 (.A(d), .Y(d_n));
AOI22_X1 u2 (.A1(a), .A2(b), .B1(c), .B2(d_n), .Y(result_n));
INV_X1 u3 (.A(result_n), .Y(result));
Mapping for Sequential Logic
D Flip-Flop
// RTL
always @(posedge clk)
q <= d;
// Mapped
DFF_X1 u1 (.D(d), .CK(clk), .Q(q));
Flip-Flop with Enable
// RTL
always @(posedge clk)
if (enable)
q <= d;
// Mapped Option 1: Mux + DFF
MUX2_X1 u1 (.A(q), .B(d), .S(enable), .Y(d_muxed));
DFF_X1 u2 (.D(d_muxed), .CK(clk), .Q(q));
// Mapped Option 2: DFF with enable
DFFE_X1 u1 (.D(d), .CK(clk), .EN(enable), .Q(q));
The tool chooses based on what's available in the library and which is more efficient.
Optimization Goals: The Three-Way Trade-off
Synthesis must balance three competing objectives: area, power, and timing. Improving one often degrades others.
Area Optimization
Goal: Minimize total silicon area (die size)
Why It Matters
- Smaller die → More dies per wafer → Lower manufacturing cost
- Smaller area → Shorter wires → Better timing and power
- Enables higher integration (more features on chip)
Techniques
- Resource sharing: Reuse functional units across time
- Smaller drive strengths: Use X1 cells instead of X4 when possible
- Complex gates: Use AOI/OAI gates instead of simple gate combinations
- Logic minimization: Reduce gate count through Boolean optimization
Example
// RTL: Two separate adders
assign sum1 = a + b;
assign sum2 = c + d;
// Area-optimized: Shared adder (if sum1 and sum2 never needed simultaneously)
always @(*) begin
if (sel)
sum = a + b;
else
sum = c + d;
end
// Area savings: 1 adder instead of 2
Trade-offs
- Smaller cells are slower (longer delays)
- Complex gates may have limited fanout
- Resource sharing adds multiplexing overhead
Power Optimization
Goal: Minimize power consumption (both static and dynamic)
Why It Matters
- Battery life in mobile devices
- Cooling costs in data centers
- Reliability (lower temperature → longer life)
- Power delivery network design
Techniques
- Clock gating: Disable clocks to idle logic
- Lower drive strength: Smaller cells leak less and switch less power
- Reduced switching: Minimize logic transitions
- Operand isolation: Prevent glitches from propagating
Clock Gating Example
// Original: Counter always active
always @(posedge clk)
counter <= counter + 1;
// Power-optimized: Clock gating
wire gated_clk;
CKGT_X1 clock_gate (.CK(clk), .EN(enable), .CKG(gated_clk));
always @(posedge gated_clk)
counter <= counter + 1;
// Power savings: No switching when enable=0
Trade-offs
- Clock gating adds area (clock gate cells)
- Lower drive strength increases delay
- May need to sacrifice speed for power
Timing Optimization
Goal: Minimize critical path delay (maximize operating frequency)
Why It Matters
- Higher clock frequency → Better performance
- Meeting timing specifications in high-speed interfaces
- Competitive advantage in compute-intensive applications
Techniques
- Upsizing: Use larger drive strengths (X4, X8) on critical paths
- Logic restructuring: Rearrange logic to balance delays
- Buffering: Insert buffers to drive heavy loads
- Pipelining: Add registers to break long combinational paths
Timing Optimization Example
// Original: Long combinational path
assign result = ((a & b) | (c & d)) & ((e | f) & (g | h));
// Timing-optimized: Use faster gates on critical path
// Replace OR gates with NOR+INV (if NOR is faster in library)
// Use high-drive-strength gates for high-fanout nets
// Or: Pipeline the logic
always @(posedge clk) begin
stage1 <= (a & b) | (c & d);
stage2 <= (e | f) & (g | h);
result_reg <= stage1 & stage2;
end
// Trade-off: Added latency, but higher frequency possible
Trade-offs
- Larger cells consume more area and power
- Buffering adds area and power overhead
- Pipelining increases latency (clock cycles)
Multi-Objective Optimization
Real designs require balancing all three goals:
Example: Mobile SoC
- Primary: Minimize power (battery life)
- Secondary: Meet timing at 1 GHz
- Tertiary: Minimize area (cost)
Synthesis Strategy
- Start with area-focused synthesis (baseline)
- Identify critical paths not meeting 1 GHz
- Selectively upsize gates on critical paths only
- Apply clock gating to reduce power
- Iterate until all constraints met
Example: High-Performance Server CPU
- Primary: Maximize frequency (performance)
- Secondary: Manage power (cooling limits)
- Tertiary: Area less critical
Synthesis Strategy
- Aggressive timing optimization (high-drive cells)
- Pipeline deep logic for higher frequency
- Accept larger area for speed
- Power optimization in non-critical regions only
Constraint-Driven Synthesis
Modern synthesis is constraint-driven: You specify requirements, the tool finds solutions.
Typical Constraints
# Timing constraints
create_clock -period 2.0 [get_ports clk] # 500 MHz
set_max_delay 1.8 -from [all_inputs] -to [all_outputs]
# Area constraints
set_max_area 50000 # in library units
# Power constraints
set_max_dynamic_power 500 # in mW
The synthesis tool then optimizes to meet these constraints, making trade-offs automatically.
The Synthesis Quality Metrics
After synthesis, you evaluate results using key metrics:
Area Metrics
Total cell area: 45,234 um²
Cell count: 12,456 cells
Sequential cells: 2,345 (18.8%)
Combinational cells: 10,111 (81.2%)
Timing Metrics
Critical path delay: 1.85ns
Clock period: 2.0ns
Slack: 0.15ns (MET)
Number of failing paths: 0
Power Metrics
Leakage power: 2.5 mW
Dynamic power: 485 mW
Total power: 487.5 mW
Clock network power: 145 mW (29.8%)
Quality of Results (QoR)
A subjective assessment comparing:
- Did it meet timing?
- Is area reasonable?
- Is power acceptable?
- How much margin/slack exists?
Good QoR means the design meets all constraints with reasonable margin.
Yosys in the Synthesis Landscape
Yosys (Yosys Open SYnthesis Suite) is an open-source synthesis tool that implements all these concepts:
Advantages
- Free and open-source
- Excellent for learning synthesis fundamentals
- Scriptable and extensible
- Strong academic and hobbyist community
- Supports various FPGA and ASIC flows
Limitations
- Less optimized than commercial tools (Synopsys Design Compiler, Cadence Genus)
- Smaller cell library support
- Fewer advanced optimization algorithms
Where Yosys Excels
- Educational use (understanding synthesis)
- FPGA design (via nextpnr, Project IceStorm)
- Small to medium ASIC projects
- Prototyping and experimentation
In the following modules, we'll use Yosys to explore synthesis hands-on, learning by doing while building on these fundamental concepts.
Summary
Logic synthesis is the critical transformation from RTL to gates:
- Synthesis converts behavioral RTL descriptions into gate-level netlists
- The process includes parsing, optimization, technology mapping, and netlist generation
- Technology mapping selects specific library cells to implement Boolean functions
- Three optimization goals (area, power, timing) must be balanced
- Constraint-driven synthesis lets designers specify requirements and trade-offs
- Yosys provides an open-source platform for learning and applying synthesis
Understanding synthesis fundamentals enables you to:
- Write better, more synthesizable RTL
- Understand synthesis reports and quality metrics
- Debug timing and area problems effectively
- Make informed architectural decisions
- Work effectively with synthesis tools
With this foundation, you're ready to perform actual synthesis using Yosys, exploring hands-on how RTL transforms into gates and learning to optimize designs for real-world constraints.
