Power Information in Liberty Files

The Other Half of the Design Equation

You've mastered timing—understanding delays, transitions, and how cells respond under different conditions. But there's another critical dimension to digital design: power consumption. A chip that meets timing but consumes too much power is just as useless as one that's too slow. Power determines battery life, cooling requirements, reliability, and ultimately whether your design is practical or just theoretical.

Liberty files contain detailed power models alongside timing data. Every cell has been characterized not just for speed, but for how much energy it consumes during switching and how much it leaks when idle. Understanding power information in Liberty files is essential for modern design, where power budgets are often as constraining as timing budgets.

The Fundamental Power Equation

Before diving into Liberty specifics, let's establish the framework:

Total Power = Static Power + Dynamic Power

Each component is modeled differently in Liberty files, and understanding the distinction is crucial.

Static Power: The Silent Drain

What Is Static Power?

Static power (also called leakage power) is consumed continuously, regardless of whether the circuit is switching. Even when your chip sits idle, current leaks through transistors, consuming power and generating heat.

Physical Sources of Leakage

Subthreshold Leakage
Transistors aren't perfect switches. Even when "off" (Vgs < Vth), a small current flows from drain to source. This subthreshold current increases exponentially as:

• Threshold voltage decreases (faster transistors leak more)
• Temperature increases (hotter chips leak more)
• Gate length decreases (advanced nodes leak more)

Gate Leakage
In modern processes with ultra-thin gate oxides, current tunnels directly through the gate dielectric. This was negligible in older technologies but dominates in sub-20nm nodes.

Junction Leakage
Reverse-biased P-N junctions at source and drain regions contribute small leakage currents.

Leakage Power in Liberty Files

Basic Leakage Specification

cell (INV_X1) {
    area : 2.532;
    
    /* Single leakage value for entire cell */
    cell_leakage_power : 0.125;  // In library power units (nW)
    
    pin (A) {
        direction : input;
        capacitance : 0.0015;
    }
    
    pin (Y) {
        direction : output;
        function : "!A";
    }
}

What This Number Means
The cell leaks 0.125 nanoWatts continuously when powered, regardless of activity. For a chip with 1 million of these inverters:

Total leakage = 1,000,000 × 0.125nW = 125mW

That's just from inverters! Add all the other cells, and leakage becomes a significant portion of total power.

State-Dependent Leakage

The Reality of Leakage Variation
A cell's leakage depends on its input states. Consider an inverter:

• Input = 0 (PMOS on, NMOS off): One leakage value
• Input = 1 (PMOS off, NMOS on): Different leakage value

Advanced Leakage Modeling

cell (NAND2_X1) {
    area : 3.456;
    
    /* State-dependent leakage */
    leakage_power () {
        when : "!A & !B";
        value : 0.180;  // Both inputs low
    }
    
    leakage_power () {
        when : "!A & B";
        value : 0.195;  // A low, B high
    }
    
    leakage_power () {
        when : "A & !B";
        value : 0.195;  // A high, B low
    }
    
    leakage_power () {
        when : "A & B";
        value : 0.220;  // Both inputs high (output low, contention)
    }
}

Why This Matters
Power analysis tools can use state-dependent leakage for more accurate estimates:

• If a NAND gate's inputs are usually both low (low leakage state), actual power is less
• If inputs are usually both high (high leakage state), actual power is more
• Vector-based power analysis can account for realistic operating states

Temperature and Voltage Sensitivity

Leakage Temperature Dependence
Leakage approximately doubles for every 10°C increase:

At 25°C:  Cell leakage = 0.125nW
At 85°C:  Cell leakage ≈ 8 × 0.125nW = 1.0nW (8× increase!)
At 125°C: Cell leakage ≈ 64 × 0.125nW = 8.0nW (64× increase!)

This is why Liberty files exist for different temperatures, and why hot corners show dramatically higher leakage.

Process Corner Impact

FF corner: Lowest Vth → Highest leakage (transistors leak more)
TT corner: Nominal Vth → Typical leakage
SS corner: Highest Vth → Lowest leakage (transistors leak less)

Critical Design Implication
Maximum leakage power analysis uses:

• FF corner (fastest process, lowest Vth)
• Maximum voltage (Vdd + 10%)
• Maximum temperature (125°C)

This corner combination can show 100× more leakage than typical conditions!

Dynamic Power: The Energy of Activity

Dynamic power is consumed when circuits switch—charging and discharging capacitances as signals transition between 0 and 1.

The Classic Dynamic Power Equation

P_dynamic = α × C × V² × f

Where:
  α = activity factor (how often signals switch)
  C = capacitance being switched
  V = supply voltage
  f = clock frequency

Liberty files model dynamic power through two components: internal power and switching power.

Internal Power: Inside the Cell

What Is Internal Power?

Internal power is consumed within the cell during a transition—the energy required to switch internal nodes and drive output stages.

Physical Sources

• Charging/discharging internal node capacitances
• Short-circuit current when PMOS and NMOS are briefly both on during transitions
• Current required to drive the output load

Internal Power Tables

Like timing, internal power is characterized across input transitions and output loads:

cell (INV_X1) {
    pin (A) {
        direction : input;
        capacitance : 0.0015;
    }
    
    pin (Y) {
        direction : output;
        function : "!A";
        
        /* Internal power when A rises (Y falls) */
        internal_power () {
            related_pin : "A";
            
            /* Power consumed for rising input */
            rise_power (power_template_5x5) {
                index_1 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Input transition
                index_2 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Output load
                values ( \
                    "0.085, 0.092, 0.106, 0.134, 0.190", \
                    "0.088, 0.095, 0.109, 0.137, 0.193", \
                    "0.094, 0.101, 0.115, 0.143, 0.199", \
                    "0.106, 0.113, 0.127, 0.155, 0.211", \
                    "0.130, 0.137, 0.151, 0.179, 0.235" \
                );
            }
            
            /* Power consumed for falling input */
            fall_power (power_template_5x5) {
                index_1 ("0.01, 0.05, 0.1, 0.2, 0.4");
                index_2 ("0.01, 0.05, 0.1, 0.2, 0.4");
                values ( \
                    "0.095, 0.105, 0.125, 0.165, 0.245", \
                    "0.098, 0.108, 0.128, 0.168, 0.248", \
                    "0.104, 0.114, 0.134, 0.174, 0.254", \
                    "0.116, 0.126, 0.146, 0.186, 0.266", \
                    "0.140, 0.150, 0.170, 0.210, 0.290" \
                );
            }
        }
    }
}

Understanding the Numbers
Values are in picojoules (pJ) or library energy units. For each transition:

• Larger input transitions → more internal power (longer short-circuit current)
• Larger output loads → more internal power (more drive current needed)

Example Calculation
If an inverter switches with:

• Input transition: 0.1ns
• Output load: 0.1pF
• From fall_power table: 0.134 pJ per transition

If this inverter switches 100 MHz (100 million transitions per second):

Power = Energy × Frequency
      = 0.134 pJ × 100 MHz
      = 0.0134 mW = 13.4 μW

Short-Circuit Current

The Physical Phenomenon
During a transition, there's a brief moment when both PMOS and PMOS transistors are on:

Input at Vdd/2 (mid-transition):
  PMOS Vgs = -Vdd/2 (partially on)
  NMOS Vgs = +Vdd/2 (partially on)
  Direct path from Vdd to ground!

This "short-circuit" current:

• Increases with slower input transitions (more time in the danger zone)
• Doesn't do useful work (doesn't charge output)
• Pure power loss as heat

Impact on Internal Power
Notice in the power tables that slower input transitions (larger index_1 values) show higher internal power—this is largely short-circuit current.

Design Implications

• Keep transitions fast (but not so fast it causes signal integrity issues)
• Matched rise/fall times reduce short-circuit current
• This is why transition time constraints exist in libraries

Switching Power: Charging the Load

What Is Switching Power?

Switching power is the energy required to charge and discharge the capacitive load connected to the output pin.

The Physics
When an output transitions high:

Energy stored in capacitor = ½ × C × V²

When transitioning low, this energy discharges to ground (converted to heat).

Why Separate from Internal Power?

Different Nature

• Internal power: Depends on the cell's internal structure
• Switching power: Depends entirely on external load

Different Calculation Method
Switching power is usually calculated directly by the power analysis tool:

E_switching = ½ × C_load × V_dd²
P_switching = E_switching × f × α

Where:
  C_load = output load capacitance (from parasitic extraction)
  V_dd = supply voltage
  f = clock frequency
  α = switching activity (0.0 to 1.0)

Liberty Representation
Some Liberty files don't have explicit switching power tables because it's calculated from:

• Supply voltage (from operating conditions)
• Output load (from connected cells/wires)
• Activity factor (from simulation or estimation)

Advanced Switching Power Models
Modern Liberty files may include switching power tables:

pin (Y) {
    direction : output;
    
    /* Switching power */
    power () {
        related_pin : "A";
        
        /* Energy to charge output when transitioning high */
        rise_power (power_template_5x5) {
            index_1 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Input transition
            index_2 ("0.01, 0.05, 0.1, 0.2, 0.4");  // Output load
            values ( \
                "0.018, 0.090, 0.180, 0.360, 0.720", \
                "0.018, 0.090, 0.180, 0.360, 0.720", \
                "0.018, 0.090, 0.180, 0.360, 0.720", \
                "0.018, 0.090, 0.180, 0.360, 0.720", \
                "0.018, 0.090, 0.180, 0.360, 0.720" \
            );
        }
    }
}

Notice that switching power is nearly independent of input transition time (all rows similar) but scales with load (column progression).

Sequential Cell Power Models

Flip-flops and latches have more complex power behavior:

cell (DFF_X1) {
    ff ("IQ", "IQN") {
        next_state : "D";
        clocked_on : "CP";
    }
    
    /* Leakage power */
    cell_leakage_power : 0.450;
    
    pin (CP) {
        direction : input;
        capacitance : 0.0025;
        
        /* Clock pin internal power (clock tree power) */
        internal_power () {
            related_pin : "CP";
            
            /* Power per clock edge */
            rise_power (scalar) {
                values ("2.5");  // pJ per rising edge
            }
            
            fall_power (scalar) {
                values ("2.3");  // pJ per falling edge
            }
        }
    }
    
    pin (D) {
        direction : input;
        capacitance : 0.0018;
        
        /* Data pin internal power */
        internal_power () {
            related_pin : "D";
            when : "CP";  // Power when data changes and clock is high
            
            rise_power (power_template_5x5) {
                /* Tables... */
            }
            
            fall_power (power_template_5x5) {
                /* Tables... */
            }
        }
    }
    
    pin (Q) {
        direction : output;
        function : "IQ";
        
        /* Clock-to-Q internal power */
        internal_power () {
            related_pin : "CP";
            
            rise_power (power_template_5x5) {
                /* Tables... */
            }
            
            fall_power (power_template_5x5) {
                /* Tables... */
            }
        }
        
        /* Data-dependent internal power */
        internal_power () {
            related_pin : "D";
            when : "CP";
            
            rise_power (power_template_5x5) {
                /* Tables... */
            }
        }
    }
}

Clock Power Components

1. Clock pin internal power: Energy to drive internal clock network
2. Clock tree switching power: Charging clock pin capacitance
3. Data-dependent power: Extra power when data actually changes

Why Clock Power Matters
Clock networks consume 30-50% of total chip power because:

• Every flip-flop's clock pin switches every cycle
• Clock trees have high fanout (large capacitance)
• Activity factor α = 1.0 (clocks always toggle)

Complete Power Analysis Example

Let's calculate total power for a simple path:

Circuit

DFF_X1 → INV_X2 → NAND2_X1 → DFF_X1

Assumptions

• Clock: 500 MHz
• Supply: 1.8V
• Temperature: 85°C (TT corner)
• Activity factor: 0.2 (signals switch 20% of the time)

Component Powers

1. Launch Flip-Flop (DFF_X1)

Leakage: 0.450 nW
Clock internal power: 2.5 pJ/edge × 500 MHz = 1.25 mW
Clock switching power: ½ × 0.0025pF × 1.8² × 500MHz = 4.05 μW
Data internal power: 0.180 pJ × 500MHz × 0.2 = 18 μW (when switching)
Q output switching: ½ × 0.025pF × 1.8² × 500MHz × 0.2 = 8.1 μW
Total: 1.28 mW

2. Inverter (INV_X2)

Leakage: 0.180 nW (negligible)
Internal power: 0.115 pJ × 500MHz × 0.2 = 11.5 μW
Switching power: ½ × 0.030pF × 1.8² × 500MHz × 0.2 = 9.72 μW
Total: 21.2 μW

3. NAND Gate (NAND2_X1)

Leakage: 0.220 nW
Internal power: 0.125 pJ × 500MHz × 0.2 = 12.5 μW
Switching power: ½ × 0.020pF × 1.8² × 500MHz × 0.2 = 6.48 μW
Total: 19.0 μW

4. Capture Flip-Flop (DFF_X1)

(Same as launch flip-flop)
Total: 1.28 mW

Path Total Power

Static (leakage): 0.450 + 0.180 + 0.220 + 0.450 = 1.3 nW
Dynamic: 1.28 + 0.021 + 0.019 + 1.28 = 2.6 mW

Total: 2.6 mW (dynamic dominates at this frequency)

Scaling to Full Chip
For a design with 100,000 similar paths:

Total power ≈ 2.6 mW × 100,000 = 260W!

This illustrates why power optimization is critical.

Power Optimization Insights from Liberty Data

Drive Strength Selection

Trade-off Analysis
Compare INV_X1 vs. INV_X4:

                    INV_X1      INV_X4
Input cap:          0.0015pF    0.0060pF (4× larger)
Internal power:     0.115pJ     0.340pJ  (3× larger)
Delay (0.1pF load): 0.107ns     0.045ns  (2.4× faster)

Decision Logic

• If timing is slack: Use smaller cell (less power)
• If timing is critical: Use larger cell (faster, but more power)
• Optimal: Use just enough drive strength to meet timing

Clock Gating Benefits

Without Clock Gating

100 flip-flops, always clocked:
Clock power = 100 × 2.5pJ × 500MHz = 125 mW

With Clock Gating (50% of time idle)

Clock power = 100 × 2.5pJ × 500MHz × 0.5 = 62.5 mW (50% savings!)

Clock gating power comes from Liberty data showing clock pin internal power.

Multi-Vt Optimization

Modern libraries offer multiple threshold voltage options:

Cell        Leakage    Delay
HVT (high)  0.050nW    0.150ns (slow, low leakage)
RVT (reg)   0.125nW    0.107ns (typical)
LVT (low)   0.320nW    0.078ns (fast, high leakage)
ULVT (ultra) 0.850nW   0.055ns (fastest, highest leakage)

Optimization Strategy

• Critical paths: Use LVT/ULVT cells (accept higher leakage for speed)
• Non-critical paths: Use HVT/RVT cells (save leakage, accept slower speed)

Power analysis tools use Liberty leakage values to compute total savings.

Power Report Interpretation

Sample Power Report

Cell Instance          Static    Dynamic   Total
----------------------------------------------------
FF1 (DFF_X1)          0.45nW    1.28mW    1.28mW
INV1 (INV_X2)         0.18nW    0.021mW   0.021mW
NAND1 (NAND2_X1)      0.22nW    0.019mW   0.019mW
FF2 (DFF_X1)          0.45nW    1.28mW    1.28mW
----------------------------------------------------
Path Total            1.30nW    2.60mW    2.60mW

Breakdown:
  Leakage Power:      1.30nW   (0.00005%)
  Internal Power:     2.18mW   (83.8%)
  Switching Power:    0.42mW   (16.2%)
----------------------------------------------------

What This Tells You

• Dynamic power dominates (typical at high frequencies)
• Clock tree (internal power of flip-flops) is the main consumer
• Leakage is negligible at room temperature
• Switching power is relatively small (light loads)

At Different Temperature
Same path at 125°C:

  Leakage Power:      80nW     (0.003%)
  Internal Power:     2.25mW   (81.5%)
  Switching Power:    0.51mW   (18.5%)
----------------------------------------------------
Total:                2.76mW

Leakage increased 60×, but still small compared to dynamic power at high frequency.

Corner-Dependent Power Analysis

Maximum Power Corner (Worst-case power consumption)

Process: FF (fast, low Vth)
Voltage: 1.98V (Vdd + 10%)
Temperature: 125°C
Result: Maximum leakage, high dynamic power

Typical Power Corner (Average power consumption)

Process: TT
Voltage: 1.80V
Temperature: 25°C
Result: Nominal leakage, typical dynamic power

Minimum Power Corner (Best-case power consumption)

Process: SS (slow, high Vth)
Voltage: 1.62V (Vdd - 10%)
Temperature: -40°C
Result: Minimum leakage, reduced dynamic power

Each corner uses different Liberty files with re-characterized power values.

Advanced Power Topics

Activity Factor Estimation

Power tools estimate α (activity factor) through:

• VCD-based: Parse value change dump from simulation
• Statistical: Propagate probabilities through logic
• Annotation: Designer-specified switching rates

Liberty data provides energy per transition; activity determines how often transitions occur.

State-Dependent Power

Some cells have different power based on input states:

leakage_power () {
    when : "A & B & C";  // All inputs high
    value : 0.380;
}

leakage_power () {
    when : "!A & !B & !C";  // All inputs low
    value : 0.185;
}

Advanced power analysis uses these for accuracy.

Power Gating

Special cells for power domain control:

cell (ISO_X1) {  // Isolation cell
    /* Special power characteristics */
    ...
}

cell (LS_X1) {  // Level shifter
    /* Operates across voltage domains */
    ...
}

These cells have unique power models in Liberty files.

Summary

Power information in Liberty files enables accurate power analysis:

• Static (leakage) power is consumed continuously and increases exponentially with temperature
• Dynamic power has two components: internal power and switching power
• Internal power is consumed within the cell during transitions
• Switching power is the energy to charge/discharge output loads
• Power tables use the same 2D lookup structure as timing tables
• Sequential cells have complex power models including clock tree power
• Corner-dependent power analysis requires different Liberty files for different PVT conditions

Understanding Liberty power models enables:

• Accurate power budgeting early in design
• Intelligent drive strength selection
• Effective clock gating and power optimization
• Meeting thermal and battery life requirements

In modern designs, power is often the limiting constraint, not timing. The detailed power information in Liberty files—from leakage values to switching energy tables—provides the foundation for the aggressive power optimization techniques that make today's billion-transistor chips practical.

With timing and power mastered, you now have complete understanding of Liberty file characterization data. The next modules will explore how to use this knowledge in real synthesis and optimization flows.