Introduction to the Skywater PDK

The Skywater 130nm Process Design Kit (SKY130 PDK) represents a watershed moment in semiconductor design—it's the first truly open-source Process Design Kit from a commercial foundry. Released in 2020 through a collaboration between Google and SkyWater Technology Foundry, this PDK democratizes chip design by providing free access to the documentation, design rules, standard cell libraries, and IP blocks needed to create manufacturable silicon.

Why This Matters:

Zero-cost access: No NDAs, no licensing fees, no restricted access
Educational opportunities: Universities can teach real-world chip design
Open-source chips: Enables open hardware movement similar to open software
Community innovation: Hundreds of developers contributing tools and designs
Real fabrication: Designs can be manufactured through programs like Google's Open MPW shuttle

What You Get:

Complete process specifications (130nm technology node)
Standard cell libraries (digital logic gates, flip-flops, etc.)
I/O pads and ESD protection circuits
Memory compilers (SRAM)
Analog/mixed-signal primitives
Design rule check (DRC) and layout versus schematic (LVS) decks
Extraction rules for parasitic analysis
SPICE models for circuit simulation

This appendix serves as your comprehensive guide to navigating the Skywater PDK ecosystem, from official documentation to community-developed tools.

1. Official Documentation Links

Core PDK Repository

Main Repository:

https://github.com/google/skywater-pdk

This is the authoritative source for the Skywater 130nm PDK. It contains:

Technology files for various EDA tools
Device models (SPICE, Verilog-A)
Design rule documentation
Layer definitions
Process specifications

Key Directories:

skywater-pdk/
├── docs/              # Documentation
├── libraries/         # Standard cell libraries
│   ├── sky130_fd_sc_hd/    # High-density standard cells
│   ├── sky130_fd_sc_hdll/  # High-density low-leakage
│   ├── sky130_fd_sc_hs/    # High-speed standard cells
│   ├── sky130_fd_sc_ms/    # Medium-speed standard cells
│   ├── sky130_fd_sc_ls/    # Low-speed standard cells
│   ├── sky130_fd_sc_lp/    # Low-power standard cells
│   └── sky130_fd_io/       # I/O cells
├── scripts/           # Helper scripts
└── LICENSE            # Apache 2.0 license

Installation:

# Clone the PDK repository
git clone https://github.com/google/skywater-pdk.git
cd skywater-pdk

# Initialize submodules
git submodule update --init libraries/sky130_fd_sc_hd/latest
git submodule update --init libraries/sky130_fd_io/latest

# The PDK is now ready to use

Official Documentation Site

Skywater PDK Documentation:

https://skywater-pdk.readthedocs.io/

This comprehensive documentation covers:

1. Getting Started Section:

Installation instructions for various operating systems
Tool setup (Magic, Netgen, OpenLane, etc.)
First design tutorial
Verification flow introduction

2. Process Specifications:

Technology Overview: 130nm node characteristics, metal layers (5 or 6 metal options)
Device Models: NMOS, PMOS parameters, corner models (tt, ss, ff)
Design Rules: Minimum widths, spacing, enclosure requirements
Metal Stack: Metal layer resistances and capacitances
Via Specifications: Contact and via dimensions

3. Standard Cell Libraries: Detailed documentation for each library variant:

Library	Description	Use Case
`sky130_fd_sc_hd`	High Density	Area-critical designs, standard performance
`sky130_fd_sc_hdll`	High Density Low Leakage	Battery-powered, low standby power
`sky130_fd_sc_hs`	High Speed	Performance-critical paths
`sky130_fd_sc_ms`	Medium Speed	Balanced performance/power
`sky130_fd_sc_ls`	Low Speed	Ultra-low power applications
`sky130_fd_sc_lp`	Low Power	Low dynamic power priority

4. Design Rule Manual (DRM):

Complete listing of all geometric design rules
Layer-by-layer specifications
Well, oxide, and poly rules
Metal density requirements
Antenna rules

Access the DRM:

https://skywater-pdk.readthedocs.io/en/main/rules.html

Liberty Files Location

Liberty timing files (.lib) are essential for synthesis and timing analysis:

Repository Structure:

skywater-pdk/libraries/sky130_fd_sc_hd/latest/timing/
├── sky130_fd_sc_hd__tt_025C_1v80.lib    # Typical corner, 25°C, 1.8V
├── sky130_fd_sc_hd__ff_100C_1v95.lib    # Fast corner, 100°C, 1.95V
├── sky130_fd_sc_hd__ss_n40C_1v60.lib    # Slow corner, -40°C, 1.6V
├── sky130_fd_sc_hd__ff_n40C_1v95.lib    # Fast corner, -40°C, 1.95V
├── sky130_fd_sc_hd__ss_100C_1v60.lib    # Slow corner, 100°C, 1.6V
└── ... (many more PVT corners)

Corner Naming Convention:

sky130_fd_sc_hd__<process>_<temp>_<voltage>.lib

process: tt (typical), ff (fast), ss (slow)
temp:    025C (25°C), n40C (-40°C), 100C (100°C)
voltage: 1v80 (1.80V), 1v95 (1.95V), 1v60 (1.60V)

Usage Example:

# In Yosys synthesis script
read_liberty skywater-pdk/libraries/sky130_fd_sc_hd/latest/timing/sky130_fd_sc_hd__tt_025C_1v80.lib

LEF Files for Physical Design

LEF (Library Exchange Format) files contain abstract physical information:

Location:

skywater-pdk/libraries/sky130_fd_sc_hd/latest/lef/
├── sky130_fd_sc_hd.lef              # Technology LEF
├── sky130_fd_sc_hd__merged.lef      # Merged tech + cell LEFs
└── sky130_ef_sc_hd__decap_*.lef     # Decap cells

Technology LEF vs. Cell LEF:

Technology LEF: Layer definitions, via rules, routing constraints
Cell LEF: Abstract views of standard cells (pins, blockages, site definitions)

Verilog Models

Behavioral Verilog models for functional simulation:

Location:

skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/
├── and2/
│   └── sky130_fd_sc_hd__and2_1.v
├── nand2/
│   └── sky130_fd_sc_hd__nand2_1.v
└── ... (one directory per cell)

Consolidated Verilog:

skywater-pdk/libraries/sky130_fd_sc_hd/latest/verilog/
└── sky130_fd_sc_hd.v    # All cells in single file

Usage:

# Simulate with Icarus Verilog
iverilog -o simv \
  skywater-pdk/libraries/sky130_fd_sc_hd/latest/verilog/sky130_fd_sc_hd.v \
  design.v \
  testbench.v

SPICE Models

For analog and transistor-level simulation:

Location:

skywater-pdk/libraries/sky130_fd_pr/latest/models/
├── sky130.lib.spice                 # Main model file
├── corners/
│   ├── tt.spice                     # Typical corner
│   ├── ff.spice                     # Fast corner
│   └── ss.spice                     # Slow corner
└── parameters/

Using in ngspice:

* Include SKY130 models
.lib "skywater-pdk/libraries/sky130_fd_pr/latest/models/sky130.lib.spice" tt

* Your circuit here
M1 drain gate source bulk sky130_fd_pr__nfet_01v8 W=1u L=0.15u

2. Cell Library Browsing Tools

Official Skywater PDK Datasheet

Online Cell Browser:

https://antmicro-skywater-pdk-docs.readthedocs.io/

This interactive documentation provides:

Searchable cell database
Detailed cell specifications
Timing characteristics
Power consumption data
Area information
Pin descriptions
Truth tables for combinational logic
Timing diagrams

Example Cell Page Features: For sky130_fd_sc_hd__and2_1:

Functional Description: 2-input AND gate
Truth Table: Complete logic function
Pin Capacitances: Input loading
Timing Arcs: Propagation delays for each input-output pair
Power Characteristics: Static and dynamic power
Area: Cell footprint
Schematic: Transistor-level implementation
Symbol: Logic symbol for schematics

LibreCell - Standard Cell Generator

Repository:

https://github.com/librecell-suite

LibreCell is a suite of tools for working with standard cell libraries:

Components:

LibreCell-Layout: Automatic standard cell layout generation
LibreCell-Lib: Liberty file generation and characterization
LibreCell-Common: Shared utilities

Use Cases:

Create custom standard cells
Characterize existing layouts
Generate Liberty timing files
Modify cell libraries for specific needs

Installation:

# Install via pip
pip install librecell-layout librecell-lib

# Or clone from source
git clone https://github.com/librecell-suite/librecell-layout.git
cd librecell-layout
pip install -e .

Basic Usage:

# Generate a cell layout
lcell-gen --tech-file sky130.tech --cell-file and2.yaml --output and2.gds

# Characterize a cell
lclib-characterize --cell and2.gds --tech sky130 --output and2.lib

Magic VLSI Layout Tool

Website:

http://opencircuitdesign.com/magic/

Magic is the primary layout tool for Skywater PDK:

Installation:

# Ubuntu/Debian
sudo apt-get install magic

# From source
git clone https://github.com/RTimothyEdwards/magic.git
cd magic
./configure
make
sudo make install

Viewing Skywater Cells:

# Start Magic with SKY130 tech file
magic -T skywater-pdk/libraries/sky130A/libs.tech/magic/sky130A.tech

# In Magic console, load a cell
magic> load sky130_fd_sc_hd__and2_1

# View the layout
magic> zoom full
magic> grid 0.005um

# Extract cell information
magic> extract all
magic> ext2spice

Magic Commands for Cell Exploration:

# Load technology
load sky130_fd_sc_hd__nand2_1

# Measure features
measure width
measure height

# View different layers
see no *        # Hide all layers
see metal1      # Show only metal1
see li1         # Show local interconnect
see psdm        # Show P+ implant

# Cross-section view
xload sky130_fd_sc_hd__nand2_1
cross section

# DRC check
drc check
drc why

Klayout - Layout Viewer

Website:

https://www.klayout.de/

KLayout is a powerful layout viewer with Skywater PDK support:

Installation:

# Ubuntu/Debian
sudo apt-get install klayout

# Download from website (all platforms)
# https://www.klayout.de/build.html

Loading Skywater Layouts:

# Open a GDS file
klayout skywater-pdk/libraries/sky130_fd_sc_hd/latest/gds/sky130_fd_sc_hd.gds

# Or use Magic-generated GDS
magic -T sky130A.tech -noconsole << EOF
load sky130_fd_sc_hd__and2_1
gds write and2.gds
quit
EOF

klayout and2.gds

KLayout Features for Cell Analysis:

Layer display: Visualize all metal, poly, diffusion layers
Measurement tools: Measure distances, areas
Cross-section view: See vertical structure
DRC checking: Run design rule checks
Net tracing: Follow connections
Cell hierarchy: Navigate through hierarchical designs

Useful KLayout Shortcuts:

F2:     Zoom to full view
Shift+F2: Zoom to selected
Ctrl+F:  Find objects
R:       Ruler tool
M:       Measure
X:       Cross-section view

Cell Library Scripts

Custom Python Script for Cell Browsing:

#!/usr/bin/env python3
"""
Browse Skywater standard cell library
"""

import os
import re
from pathlib import Path

class Sky130CellBrowser:
    def __init__(self, pdk_path):
        self.pdk_path = Path(pdk_path)
        self.lib_path = self.pdk_path / "libraries"
        
    def list_libraries(self):
        """List all available standard cell libraries"""
        libs = []
        for lib_dir in self.lib_path.glob("sky130_fd_sc_*"):
            if lib_dir.is_dir():
                libs.append(lib_dir.name)
        return sorted(libs)
    
    def list_cells(self, library="sky130_fd_sc_hd"):
        """List all cells in a library"""
        cells = []
        cell_dir = self.lib_path / library / "latest" / "cells"
        
        if not cell_dir.exists():
            print(f"Error: {cell_dir} not found")
            return []
        
        for cell_path in cell_dir.iterdir():
            if cell_path.is_dir():
                cells.append(cell_path.name)
        
        return sorted(cells)
    
    def get_cell_info(self, cell_name, library="sky130_fd_sc_hd"):
        """Get detailed information about a cell"""
        
        cell_dir = self.lib_path / library / "latest" / "cells" / cell_name
        
        info = {
            'name': cell_name,
            'library': library,
            'files': []
        }
        
        # Find available files
        if cell_dir.exists():
            for file in cell_dir.iterdir():
                info['files'].append(file.name)
        
        # Parse Verilog for functionality
        verilog_file = cell_dir / f"{library}__{cell_name}.v"
        if verilog_file.exists():
            with open(verilog_file, 'r') as f:
                content = f.read()
                # Extract module definition
                module_match = re.search(r'module\s+\w+\s*\((.*?)\);', 
                                       content, re.DOTALL)
                if module_match:
                    info['ports'] = module_match.group(1)
        
        return info
    
    def search_cells(self, pattern, library="sky130_fd_sc_hd"):
        """Search for cells matching a pattern"""
        cells = self.list_cells(library)
        matching = [c for c in cells if pattern.lower() in c.lower()]
        return matching
    
    def print_cell_summary(self, cell_name, library="sky130_fd_sc_hd"):
        """Print a summary of cell information"""
        info = self.get_cell_info(cell_name, library)
        
        print(f"\nCell: {info['name']}")
        print(f"Library: {info['library']}")
        print(f"Available files:")
        for f in info['files']:
            print(f"  - {f}")
        
        if 'ports' in info:
            print(f"\nPorts:")
            print(f"  {info['ports']}")

# Example usage
if __name__ == "__main__":
    browser = Sky130CellBrowser("path/to/skywater-pdk")
    
    # List all libraries
    print("Available libraries:")
    for lib in browser.list_libraries():
        print(f"  - {lib}")
    
    # Search for AND gates
    print("\nAND gates in sky130_fd_sc_hd:")
    and_gates = browser.search_cells("and", "sky130_fd_sc_hd")
    for gate in and_gates[:5]:  # Show first 5
        print(f"  - {gate}")
    
    # Get details on specific cell
    browser.print_cell_summary("and2_1")

Save as sky130_browser.py and use:

python3 sky130_browser.py

3. Community Resources

OpenLane - Complete RTL-to-GDSII Flow

Repository:

https://github.com/The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL-to-GDSII flow specifically designed for Skywater 130nm:

What It Includes:

Yosys (synthesis)
OpenROAD (place and route)
Magic (DRC/LVS)
KLayout (GDS manipulation)
Pre-configured for SKY130 PDK

Installation via Docker:

# Pull OpenLane Docker image
docker pull efabless/openlane:latest

# Run OpenLane
docker run -it -v $(pwd):/workspace efabless/openlane:latest

Installation from Source:

# Clone repository
git clone https://github.com/The-OpenROAD-Project/OpenLane.git
cd OpenLane

# Install dependencies
make install

# Test installation
make test

Running a Design:

# Create design directory structure
make mount
./flow.tcl -design <design_name> -tag <run_name>

# Example
./flow.tcl -design spm -tag trial_run

OpenLane Results:

runs/<run_name>/
├── results/
│   ├── synthesis/     # Synthesized netlist
│   ├── floorplan/     # Floorplan DEF
│   ├── placement/     # Placed design
│   ├── routing/       # Routed design
│   ├── magic/         # DRC/LVS reports
│   └── gds/           # Final GDSII
└── reports/           # Detailed reports

Caravel - SoC Platform

Repository:

https://github.com/efabless/caravel

Caravel is a template SoC for SKY130 that provides:

RISC-V processor (PicoRV32)
GPIO and peripheral interfaces
Management core
User project area for custom logic
Pre-verified I/O and power structures

Purpose:

Rapid prototyping of custom chips
Google Open MPW shuttle submission template
Learning complete SoC design
Integration example for custom blocks

Using Caravel:

# Clone Caravel
git clone https://github.com/efabless/caravel.git
cd caravel

# Initialize user project area
make install

# Add your design to user_proj_example/
cd openlane/user_proj_example/
# Edit config.tcl for your design parameters

# Run synthesis and place-and-route
make user_proj_example

# Run full SoC verification
make verify

Efabless Platform

Website:

https://efabless.com/
https://platform.efabless.com/

Efabless provides:

1. Open MPW Shuttle Program:

Free fabrication runs sponsored by Google
Submit designs using SKY130 PDK
Receive physical chips (40 dies per project)
Multiple shuttles per year

2. Platform Features:

Design submission portal
Pre-check validation tools
Community design gallery
Tutorial and documentation

3. chipIgnite Program:

Commercial fabrication platform
SKY130 and other technologies
Support for production volumes

Sign Up:

https://platform.efabless.com/auth/signup

Submission Process:

Design your chip using SKY130 PDK and OpenLane
Run pre-check validation
Submit through platform before deadline
Pass design review
Receive fabricated chips (3-6 months)

Community Forums and Support

1. Skywater PDK Slack:

https://invite.skywater.tools/

Active community discussions
Design questions and answers
Tool support
Fabrication experience sharing

2. Efabless Community Forum:

https://community.efabless.com/

Design showcase
Technical discussions
Shuttle program announcements
Troubleshooting help

3. GitHub Discussions:

https://github.com/google/skywater-pdk/discussions

Official PDK discussions
Feature requests
Bug reports
Design rule clarifications

4. Reddit r/OpenSourceSilicon:

https://reddit.com/r/OpenSourceSilicon

General open-source silicon discussions
Project showcases
Learning resources

Educational Resources

1. Mohamed Kassem's SKY130 Tutorials:

https://github.com/mkaskov/sky130_mos_tutorial

Device characterization tutorials
SPICE simulation examples
Layout techniques

2. Matt Venn's Zero to ASIC Course:

https://www.zerotoasiccourse.com/

Complete course on chip design with SKY130
Video tutorials
Hands-on projects
Active community

3. FOSSi Foundation Resources:

https://www.fossi-foundation.org/

Free and Open Source Silicon Foundation
Conference talks
Educational materials
Community events

4. Tiny Tapeout:

https://tinytapeout.com/

Low-cost way to learn chip design
Educational platform for SKY130
Shared die for multiple designs
Excellent for beginners

Example Designs Repository

Repository:

https://github.com/efabless/caravel_user_project

Contains example designs demonstrating:

Digital design flow
Analog design integration
Mixed-signal projects
SoC integration techniques

Notable Example Projects:

# StriVe processor variants
https://github.com/efabless/caravel_mgmt_soc_litex

# Analog examples
https://github.com/efabless/caravel_analog_user

# Counter example (great for learning)
https://github.com/efabless/caravel_user_project_analog

Tool Integration Examples

Yosys + OpenLane Integration:

# config.tcl for OpenLane design
set ::env(DESIGN_NAME) my_design
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
set ::env(CLOCK_PORT) "clk"
set ::env(CLOCK_PERIOD) "10"

# Use SKY130 standard cells
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"

# Synthesis strategy
set ::env(SYNTH_STRATEGY) "AREA 0"
set ::env(SYNTH_BUFFERING) 1
set ::env(SYNTH_SIZING) 1

Magic DRC/LVS Script:

# drc_check.tcl
# Load technology
tech load sky130A

# Load design
gds read design.gds

# Run DRC
load design
drc check
drc catchup
set drcresult [drc listall why]
puts "DRC violations: [llength $drcresult]"

# Output results
drc save drc_results.txt

Community Design Showcase

Notable Open-Source Chips with SKY130:

OpenRAM - Memory compiler
- Repository: https://github.com/VLSIDA/OpenRAM
- Generates SRAM blocks
SERV - Award-winning bit-serial RISC-V CPU
- Repository: https://github.com/olofk/serv
- Ultra-compact processor
PicoRV32 - Small RISC-V core
- Repository: https://github.com/YosysHQ/picorv32
- Used in Caravel management core
OpenPower - POWER ISA cores
- Repository: https://github.com/openpower
- Advanced processor designs
Various Accelerators:
- Neural network accelerators
- Cryptographic engines
- DSP cores
- Custom interfaces

Browse Submitted Designs:

https://platform.efabless.com/projects/public

Getting Started with SKY130 PDK

Quick Start Guide

1. Install PDK:

# Install OpenLane (includes PDK)
git clone https://github.com/The-OpenROAD-Project/OpenLane.git
cd OpenLane
make

# Or install PDK separately
git clone https://github.com/google/skywater-pdk.git
cd skywater-pdk
git submodule update --init libraries/sky130_fd_sc_hd/latest

2. Create Simple Design:

// counter.v - Simple 8-bit counter
module counter(
    input wire clk,
    input wire rst,
    output reg [7:0] count
);
    always @(posedge clk or posedge rst) begin
        if (rst)
            count <= 8'b0;
        else
            count <= count + 1;
    end
endmodule

3. Synthesize with Yosys:

yosys -p "
    read_verilog counter.v;
    synth -top counter;
    dfflibmap -liberty skywater-pdk/libraries/sky130_fd_sc_hd/latest/timing/sky130_fd_sc_hd__tt_025C_1v80.lib;
    abc -liberty skywater-pdk/libraries/sky130_fd_sc_hd/latest/timing/sky130_fd_sc_hd__tt_025C_1v80.lib;
    write_verilog counter_synth.v
"

4. View Synthesized Cells:

# Check what cells were used
grep "sky130_fd_sc_hd__" counter_synth.v

# Expected cells:
# - sky130_fd_sc_hd__dfxtp_1 (D flip-flops)
# - sky130_fd_sc_hd__fa_1 (full adders)
# - sky130_fd_sc_hd__and2_1 (AND gates)
# etc.

Best Practices for SKY130 Designs

1. Start Simple:

Begin with small digital blocks
Use sky130_fd_sc_hd library (high density, general purpose)
Verify with open-source tools before committing to fabrication

2. Leverage Community:

Join Slack channels for quick help
Review example designs before starting
Participate in Tiny Tapeout for learning

3. Use OpenLane Flow:

Don't try to manually configure all tools
OpenLane handles 90% of the complexity
Customize only when necessary

4. Validate Thoroughly:

Run DRC and LVS checks
Simulate at multiple corners (tt, ss, ff)
Use pre-check tools before shuttle submission

5. Document Your Design:

Include comprehensive README
Provide testbenches
Document any custom scripts or flows

Troubleshooting Resources

Common Issues and Solutions:

Issue	Solution	Resource
PDK not found	Check submodule initialization	`git submodule update --init`
Timing violations	Adjust constraints, use faster cells	OpenLane timing guides
DRC errors	Review design rules, check Magic output	SKY130 DRM
Missing libraries	Install dependencies	OpenLane installation guide
Synthesis errors	Check Verilog syntax, library mapping	Yosys documentation

Where to Get Help:

Check GitHub issues first
Search Slack channel history
Post detailed questions with:
- Error messages
- Tool versions
- Minimal reproducible example
Be patient - community support is volunteer-based

Conclusion

The Skywater 130nm PDK represents a revolutionary development in semiconductor design education and open-source hardware. With comprehensive documentation, powerful tooling, and an active community, it's never been more accessible to design real, manufacturable chips.

Your Journey with SKY130:

Beginner Path:

Complete Zero to ASIC course
Synthesize simple designs with Yosys
Run designs through OpenLane
Submit to Tiny Tapeout

Intermediate Path:

Design custom standard cells
Integrate analog components
Create complete SoCs with Caravel
Submit to Open MPW program

Advanced Path:

Contribute to PDK development
Develop new EDA tools
Create novel processor architectures
Push the boundaries of open silicon

Resources to Bookmark:

Skywater PDK Repository: https://github.com/google/skywater-pdk
Documentation: https://skywater-pdk.readthedocs.io/
OpenLane: https://github.com/The-OpenROAD-Project/OpenLane
Efabless Platform: https://platform.efabless.com/
Community Slack: https://invite.skywater.tools/

The barrier to chip design has never been lower. The tools are free, the documentation is comprehensive, and the community is welcoming. Whether you're a student, hobbyist, or professional engineer, the Skywater PDK provides everything needed to design real silicon.

Start exploring, start designing, and join the open-source silicon revolution!

Quick Links Summary:

Official:

Main PDK: https://github.com/google/skywater-pdk
Documentation: https://skywater-pdk.readthedocs.io/
Cell Docs: https://antmicro-skywater-pdk-docs.readthedocs.io/

Tools:

OpenLane: https://github.com/The-OpenROAD-Project/OpenLane
Magic: http://opencircuitdesign.com/magic/
KLayout: https://www.klayout.de/

Community:

Slack: https://invite.skywater.tools/
Forum: https://community.efabless.com/
Reddit: https://reddit.com/r/OpenSourceSilicon

Learning:

Zero to ASIC: https://www.zerotoasiccourse.com/
Tiny Tapeout: https://tinytapeout.com/
Efabless: https://efabless.com/

Fabrication:

Open MPW: https://platform.efabless.com/
Design Gallery: https://platform.efabless.com/projects/public

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Skywater PDK Resources

Introduction to the Skywater PDK

1. Official Documentation Links

Core PDK Repository

Official Documentation Site

Liberty Files Location

LEF Files for Physical Design

Verilog Models

SPICE Models

2. Cell Library Browsing Tools

Official Skywater PDK Datasheet

LibreCell - Standard Cell Generator

Magic VLSI Layout Tool

Klayout - Layout Viewer

Cell Library Scripts

3. Community Resources

OpenLane - Complete RTL-to-GDSII Flow

Caravel - SoC Platform

Efabless Platform

Community Forums and Support

Educational Resources

Example Designs Repository

Tool Integration Examples

Community Design Showcase

Getting Started with SKY130 PDK

Quick Start Guide

Best Practices for SKY130 Designs

Troubleshooting Resources

Conclusion

Quiz

Quick Index

Search Results

Skywater PDK Resources

Introduction to the Skywater PDK

1. Official Documentation Links

Core PDK Repository

Official Documentation Site

Liberty Files Location

LEF Files for Physical Design

Verilog Models

SPICE Models

2. Cell Library Browsing Tools

Official Skywater PDK Datasheet

LibreCell - Standard Cell Generator

Magic VLSI Layout Tool

Klayout - Layout Viewer

Cell Library Scripts

3. Community Resources

OpenLane - Complete RTL-to-GDSII Flow

Caravel - SoC Platform

Efabless Platform

Community Forums and Support

Educational Resources

Example Designs Repository

Tool Integration Examples

Community Design Showcase

Getting Started with SKY130 PDK

Quick Start Guide

Best Practices for SKY130 Designs

Troubleshooting Resources

Conclusion

Quiz