Introduction: Reading the Blueprints

You've learned that standard cells are the building blocks of digital chip design, and you understand the naming conventions and different library variants. But how do you actually understand what a specific cell does, how large it is, how fast it operates, and how much power it consumes? This is where cell documentation becomes critical.

Every standard cell comes with extensive documentation—datasheets, timing models, physical layouts, and characterization data. Learning to read and interpret this documentation is like learning to read blueprints in construction. It tells you not just what a cell does logically, but its physical dimensions, electrical characteristics, and performance across different conditions.

In this module, we'll explore how to navigate cell documentation in the Skywater 130nm PDK, understand what the numbers mean, interpret timing and power data, and work with special-purpose cells that don't implement logic but are essential for chip functionality.

Understanding Liberty Timing Files (.lib)

The most important documentation for synthesis and timing analysis is the Liberty format (.lib) file. This industry-standard format describes every electrical characteristic of every cell in a library.

Liberty File Structure

A Liberty file is a text-based database organized hierarchically:

library (sky130_fd_sc_hd__tt_025C_1v80) {
    technology : cmos;
    delay_model : table_lookup;
    
    /* Library-level defaults */
    voltage : 1.80;
    temperature : 25;
    
    /* Units */
    time_unit : "1ns";
    voltage_unit : "1V";
    current_unit : "1mA";
    capacitive_load_unit (1, pf);
    
    /* Operating conditions */
    operating_conditions (tt_025C_1v80) {
        process : 1.0;
        temperature : 25;
        voltage : 1.80;
    }
    
    /* Individual cell descriptions */
    cell (sky130_fd_sc_hd__inv_1) {
        /* Cell characteristics */
    }
    
    cell (sky130_fd_sc_hd__nand2_1) {
        /* Cell characteristics */
    }
    
    /* ... hundreds more cells ... */
}

The library header defines process corner, voltage, and temperature—critical for understanding under what conditions the timing data applies.

Process Corners Explained

The filename sky130_fd_sc_hd__tt_025C_1v80.lib encodes operating conditions:

tt (typical-typical): Both NMOS and PMOS transistors have typical parameters. This represents average manufacturing and nominal operating conditions.

ss (slow-slow): Both transistor types are slow. Worst-case for timing (slowest operation). Used to verify setup time constraints.

ff (fast-fast): Both transistor types are fast. Worst-case for hold time violations and power. Used to verify minimum delays.

sf / fs (slow-fast, fast-slow): Mixed corners where one transistor type is fast and the other slow. These check for asymmetric behavior.

025C / 100C / -40C: Operating temperature. Transistors are faster when cold, slower when hot.

1v80 / 1v95 / 1v65: Supply voltage. Higher voltage means faster operation but more power; lower voltage saves power but reduces speed.

For comprehensive verification, you analyze your design across multiple corners to ensure it works under all conditions.

Reading a Cell Entry

Let's examine a typical cell description for a simple inverter:

cell (sky130_fd_sc_hd__inv_1) {
    area : 1.0688;  /* Square microns */
    
    cell_leakage_power : 0.0021;  /* Microwatts */
    
    pg_pin(VPWR) {
        pg_type : primary_power;
        voltage_name : VPWR;
    }
    
    pg_pin(VGND) {
        pg_type : primary_ground;
        voltage_name : VGND;
    }
    
    pin (A) {
        direction : input;
        capacitance : 0.0015;  /* Picofarads */
        
        /* More timing info... */
    }
    
    pin (Y) {
        direction : output;
        function : "!A";  /* Output = NOT(A) */
        
        max_capacitance : 0.50;  /* Max load this pin can drive */
        
        timing () {
            related_pin : "A";
            timing_sense : negative_unate;  /* A↑ causes Y↓ */
            
            cell_rise (template_1) {
                /* Lookup table for output rising delay */
                index_1 ("0.005, 0.01, 0.02, 0.05, 0.1");  /* Input transition */
                index_2 ("0.005, 0.01, 0.02, 0.05, 0.1");  /* Output load */
                values ( \
                  "0.012, 0.015, 0.021, 0.039, 0.071", \
                  "0.014, 0.017, 0.023, 0.041, 0.073", \
                  "0.018, 0.021, 0.027, 0.045, 0.077", \
                  "0.028, 0.031, 0.037, 0.054, 0.086", \
                  "0.045, 0.048, 0.054, 0.071, 0.103"  \
                );
            }
            
            /* Similar tables for cell_fall, rise_transition, fall_transition */
        }
        
        internal_power () {
            related_pin : "A";
            
            rise_power (template_1) {
                /* Power consumption lookup table */
            }
        }
    }
}

Let's decode the key information:

Area: 1.0688 square microns. This inverter occupies about 1.07 µm² of silicon. Synthesis tools use this for area estimation and optimization.

Cell Leakage Power: 0.0021 µW. This is the static power consumption when the cell is idle (no switching). For millions of gates, leakage adds up.

Pin Capacitance: Input A has 0.0015 pF of capacitance. This is the load this inverter presents to whatever drives it. Smaller is better—less capacitance means the upstream driver can switch faster.

Max Capacitance: Output Y can drive up to 0.50 pF. Beyond this, you need a stronger cell (like inv_2 or inv_4).

Function: !A means the output is the logical inversion of input A. Simple, but for complex gates, this Boolean expression defines the logic.

Interpreting Timing Tables

The cell_rise table is crucial. It's a 2D lookup table:

• Index 1 (rows): Input transition time (how fast the input changes). Faster input transitions generally produce faster outputs.
• Index 2 (columns): Output load capacitance (wire and downstream gate capacitance). Larger loads slow down the output.
• Values: Propagation delay in nanoseconds.

Example interpretation: If input A transitions in 0.01ns and output Y drives 0.02pF load, the cell_rise delay is 0.017ns (17 picoseconds).

Synthesis and STA tools interpolate these tables for actual operating conditions. Similar tables exist for:

• cell_fall: Delay when output falls (high to low)
• rise_transition: How long the output takes to rise
• fall_transition: How long the output takes to fall

Timing Sense: negative_unate means when input rises, output falls (and vice versa). For a buffer, it would be positive_unate. For XOR gates, it's non_unate (output can go either direction).

Power Tables

Internal power tables describe dynamic power—energy consumed when the cell switches:

rise_power (template_1) {
    index_1 ("0.005, 0.01, 0.02, 0.05, 0.1");
    index_2 ("0.005, 0.01, 0.02, 0.05, 0.1");
    values ( \
      "0.0008, 0.0012, 0.0019, 0.0035, 0.0058", \
      /* ... more rows ... */
    );
}

Values are in microwatts per switching event. Multiply by switching frequency to get average power consumption.

Total Power Calculation:

• Static power (leakage): Always present
• Dynamic power: Depends on switching activity
• Total = Leakage + (Energy per switch × Switch frequency)

Understanding Cell Footprints and Physical Layouts

While Liberty files describe electrical behavior, physical design requires understanding cell geometry.

LEF Files: The Physical Abstraction

Library Exchange Format (LEF) files provide simplified physical information for place-and-route:

MACRO sky130_fd_sc_hd__inv_1
    CLASS CORE ;
    FOREIGN sky130_fd_sc_hd__inv_1 0.0 0.0 ;
    ORIGIN 0.0 0.0 ;
    SIZE 0.92 BY 2.72 ;  /* Width × Height in microns */
    SYMMETRY X Y ;
    
    PIN A
        DIRECTION INPUT ;
        PORT
            LAYER met1 ;
            RECT 0.145 0.91 0.475 1.25 ;  /* Pin location rectangle */
        END
    END A
    
    PIN Y
        DIRECTION OUTPUT ;
        PORT
            LAYER met1 ;
            RECT 0.515 0.91 0.845 1.25 ;
        END
    END Y
    
    PIN VPWR
        DIRECTION INOUT ;
        USE POWER ;
        PORT
            LAYER met1 ;
            RECT 0.0 2.48 0.92 2.72 ;  /* Power rail at top */
        END
    END VPWR
    
    PIN VGND
        DIRECTION INOUT ;
        USE GROUND ;
        PORT
            LAYER met1 ;
            RECT 0.0 0.0 0.92 0.24 ;  /* Ground rail at bottom */
        END
    END VGND
    
    OBS  /* Routing obstructions */
        LAYER met1 ;
        RECT 0.08 0.24 0.84 0.91 ;  /* Can't route through cell here */
    END
END sky130_fd_sc_hd__inv_1

Key information:

SIZE: 0.92 µm wide × 2.72 µm tall. All hd cells are 2.72 µm tall. Width varies by complexity.

PIN locations: Rectangle coordinates show where metal layers connect to pins. Place-and-route tools use these to plan interconnect.

SYMMETRY: X Y means the cell can be flipped horizontally or vertically without changing function. This gives place-and-route tools flexibility.

OBS (obstructions): Regions where routing is blocked because cell internals occupy that space.

Visualizing Layouts with Magic VLSI

For detailed inspection, you can view actual layouts:

magic -d XR -T sky130A sky130_fd_sc_hd__inv_1.mag

Magic VLSI Layout tool displays:

• Transistor shapes (polysilicon gates, diffusion regions)
• Metal layers (M1-M5)
• Contacts and vias connecting layers
• Well and substrate regions

This level of detail is usually unnecessary for digital design but invaluable for understanding how cells are constructed and debugging layout issues.

Cell Height and Row Structure

Standard cells are placed in horizontal rows with alternating orientations:

Row 0: [cell][cell][cell]  VDD at top, GND at bottom, normal orientation
Row 1: [cell][cell][cell]  VDD at top, GND at bottom, flipped vertically
Row 2: [cell][cell][cell]  Normal orientation
...

When cells in adjacent rows are flipped, their power rails abut, forming continuous VDD and GND stripes. This automatic power distribution is a key advantage of standard cell design.

Power, Area, and Delay Tradeoffs

Understanding cell characteristics helps you make informed design decisions.

The Iron Triangle: Power, Area, Speed

These three metrics are fundamentally in tension:

Fast cells (high drive strength):

• Larger area (bigger transistors)
• Higher power (more capacitance to charge/discharge)
• Better performance

Small cells (low drive strength):

• Minimal area
• Lower power
• Slower performance

Low-power cells (high-threshold voltage):

• Similar area
• Minimum leakage
• Slowest performance

Reading Datasheet Comparisons

Let's compare three inverter variants from the hd library:

Observations:

• inv_2 is 43% larger than inv_1 but 28% faster
• inv_4 is 80% larger than inv_2 but only 22% faster (diminishing returns)
• Leakage doubles with each strength increase (roughly)
• Drive capability doubles with each strength increase

Design Implication: Use weak cells by default, strong cells only on critical paths or heavy loads.

Multi-Corner Analysis

Real designs must work across all conditions. Consider a critical path:

The ss corner fails timing! Options:

1. Upsize cells on this path (increase drive strength)
2. Reduce logic depth (restructure the path)
3. Relax clock frequency requirement
4. Use faster library variant (ms instead of hd)

Multi-corner analysis ensures robust designs that work reliably in all operating conditions.

Special Purpose Cells

Not all cells implement logic. Several special types serve infrastructure roles.

Clock Gating Cells

Clock gating reduces dynamic power by disabling clocks to idle logic:

// Without clock gating - always toggling
always @(posedge clk)
    if (enable)
        data <= new_data;

// With clock gating - clock stops when disabled
wire gated_clk = clk & enable;  // WRONG - creates glitches!

always @(posedge gated_clk)
    data <= new_data;

Simple AND gating creates glitches if enable changes during clock high. Special integrated clock gating cells (ICG) solve this:

Cell: dlclkp_1 (data latch clock gate)

    enable ----\
                AND----> gated_clk
    clk ------->|
             latch

The latch captures enable during clock low, ensuring it's stable during clock high, preventing glitches.

Usage in Liberty:

cell (sky130_fd_sc_hd__dlclkp_1) {
    area : 6.256;
    
    pin (GATE) { direction : input; }
    pin (CLK) { direction : input; }
    pin (GCLK) { 
        direction : output;
        function : "(CLK & latched_GATE)";
    }
}

Synthesis tools automatically insert these when you enable clock gating optimization.

Tie Cells

Sometimes you need to tie signals permanently high or low. Never connect directly to power/ground—this creates reliability issues. Use tie cells:

Cell: conb_1 (connect to B)

cell (sky130_fd_sc_hd__conb_1) {
    area : 2.176;
    
    pin (HI) {
        direction : output;
        function : "1";  /* Always high */
    }
    
    pin (LO) {
        direction : output;
        function : "0";  /* Always low */
    }
}

These cells provide proper drive strength and isolation for tied-off signals.

Decoupling Capacitor Cells

On-chip decoupling capacitors stabilize power supplies:

Cell: decap_4, decap_8

These cells contain large capacitors connected between VDD and GND. They:

• Store charge locally
• Reduce supply voltage droop during switching
• Filter high-frequency noise

Place-and-route tools scatter these throughout empty spaces in the floorplan.

Filler Cells

After placement, gaps exist between cells. Filler cells fill these gaps to:

Maintain Power Rails: Ensure continuous VDD/GND connections

Meet Density Rules: Foundries require minimum metal density for chemical-mechanical polishing (CMP). Fillers add dummy metal.

Well Continuity: Ensure N-well and P-well regions connect properly.

Cell: fill_1, fill_2, fill_4, fill_8

Different widths accommodate gaps of various sizes. These contain no active logic—just metal patterns and well connections.

Tap Cells

Cell: tapvpwrvgnd_1

Substrate and well tap cells prevent latchup (a destructive failure mode) by providing low-resistance paths to substrate and wells. Place-and-route tools insert these at regular intervals (typically every 20-50 µm).

Antenna Diode Cells

During manufacturing, plasma etching can charge metal wires, potentially damaging gate oxide. Antenna diodes provide discharge paths:

Cell: diode_2

These are placed by tools when needed to protect sensitive gates.

Practical Documentation Workflow

Finding Information for a Specific Cell

1. Identify the cell: From synthesis netlist or library listing
2. Open Liberty file: Search for the cell name
3. Extract key data:
   • Area for resource estimation
   • Leakage for power budgeting
   • Max capacitance for fanout limits
   • Timing tables for delay estimation
4. Check LEF file: For physical dimensions and pin locations
5. Consult datasheet PDFs: For detailed descriptions and usage notes

Example: Analyzing a Path

Suppose synthesis reports a timing violation on a path containing nand2_1 → inv_2 → dfrtp_1.

Step 1: Check each cell's timing in the Liberty file under the failing corner (e.g., ss_100C_1v65)

Step 2: Identify the bottleneck (slowest cell or highest load)

Step 3: Consider optimizations:

• Upsize slow cell (nand2_1 → nand2_2)
• Reduce fanout (if inv_2 drives many gates, add buffer)
• Restructure logic (if possible, reduce path depth)

Step 4: Re-synthesize and verify timing improvement

Conclusion: Documentation as a Design Tool

Cell documentation isn't just reference material—it's an active tool for understanding and optimizing your designs. Reading Liberty timing models helps you understand why paths fail timing. Examining physical layouts reveals area bottlenecks. Analyzing power data guides low-power optimization.

The Skywater PDK's open documentation represents a treasure trove of information typically hidden behind NDAs. Take advantage of this transparency. When synthesis results surprise you, dig into the cell characteristics. When timing fails, examine corner-specific delays. When area exceeds budgets, analyze cell footprints.

Understanding special-purpose cells—clock gates, tie cells, fillers, taps, and decaps—demystifies the "extra" cells that appear in your netlist beyond the logic you wrote. These cells don't implement your algorithm, but they're essential for a manufacturable, reliable chip.

In the next module, we'll move from understanding the PDK to actually using it, setting up Yosys for synthesis with Skywater standard cells, and transforming your RTL into gate-level netlists ready for physical implementation.